1. An apparatus for parallel calculation of prediction bits for a spatially predicted coded block pattern having an A0 bit, an A1 bit, an A2 bit, and an A3 bit, the apparatus comprising:
a storage device storing rows of bits including the spatially predicted coded block pattern, a D0 bit, an X0 bit, an X1 bit, a Y0 bit, and a Y1 bit;
a first circuit connected to the storage device for setting the A0 bit;
a second circuit connected to the storage device for setting the A2 bit;
wherein the first circuit and the second circuit operate in parallel for setting the A0 bit equal to the Y0 bit and setting the A2 bit equal to the Y1 bit if the X0 bit is equivalent to the D0 bit, otherwise setting the A0 bit equal to the X0 bit.
2. The apparatus of claim 1 wherein the storage device comprises a shift register and after a first clock cycle, the shift register is shifted and the first circuit and the second circuit are used for setting the A1 bit and the A3 bit respectively in a second clock cycle.
3. The apparatus of claim 1 wherein the first circuit comprises:
a first comparator connected to the storage device for indicating when the D0 bit and the X0 bit are equivalent; and
a first multiplexer connected to the storage device for selectively setting the A0 bit equal to the X0 bit or the Y0 bit depending on the output of the first comparator.
4. The apparatus of claim 3 wherein the second circuit comprises:
a second comparator connected to the storage device for indicating when the X0 bit and the Y0 bit are equivalent;
a first NOR-gate having inputs connected to the output of the first comparator and the output of the second comparator; and
a second multiplexer connected to the storage device for selectively setting the A2 bit equal to the Y1 bit or the X0 bit depending on the output of the first NOR-gate.
5. The apparatus of claim 1 wherein the second circuit comprises:
a second comparator connected to the storage device for indicating when the A0 bit and the Y0 bit are equivalent; and
a second multiplexer connected to the storage device for selectively setting the A2 bit equal to the Y1 bit or the A0 bit depending on the output of the second comparator.
6. The apparatus of claim 1 further comprising:
a third circuit connected to the storage device for setting the A1 bit;
a fourth circuit connected to the storage device for setting the A3 bit;
wherein the first circuit, the second circuit, the third circuit, and the fourth circuit operate in parallel.
7. The apparatus of claim 6 wherein the third circuit comprises:
a third comparator connected to the storage device for indicating when the X0 bit and the X1 bit are equivalent; and
a third multiplexer connected to the storage device for selectively setting the A1 bit equal to the X1 bit or the A0 bit depending on the output of the third comparator.
8. The apparatus of claim 7 wherein the fourth circuit comprises:
a fourth comparator connected to the storage device for indicating when the X1 bit and the A0 bit are equivalent;
a second NOR-gate having inputs connected to the output of the third comparator and the output of the fourth comparator; and
a fourth multiplexer connected to the storage device for selectively outputting the A2 bit or the X1 bit as the A3 bit depending on the output of the second NOR-gate.
9. The apparatus of claim 6 wherein the fourth circuit comprises:
a fourth comparator connected to the storage device for indicating when the A1 bit and the A0 bit are equivalent; and
a fourth multiplexer connected to the storage device for selectively setting the A3 bit equal to the A2 bit or the A1 bit depending on the output of the fourth comparator.
10. A method for parallel calculation of prediction bits in a spatially predicted coded bit pattern having an A0 bit, an A1 bit, an A2 bit, and an A3 bit, the method comprising the following step:
(a) if an X0 bit is equivalent to a D0 bit, setting the A0 bit equal to a Y0 bit and setting the A2 bit equal to a Y1 bit, otherwise setting the A0 bit equal to the X0 bit.
11. The method of claim 10 wherein step (a) further comprises if the A0 bit is not equivalent to the Y0 bit, setting the A2 bit equal to the A0 bit.
12. The method of claim 10 wherein step (a) further comprises if the X0 bit is not equivalent to the D0 bit and the Y0 bit is not equivalent to the X0 bit, setting the A2 bit equal to the X0 bit, otherwise setting the A2 bit equal to the Y1 bit.
13. The method of claim 10 further comprising the following step:
(b) if an X1 bit is equivalent to the X0 bit, setting the A1 bit equal to the A0 bit and setting the A3 bit equal to the A2 bit, otherwise setting the A1 bit equal to the X1 bit.
14. The method of claim 13 wherein step (b) further comprises if the A1 bit is not equivalent to the A0 bit, setting the A3 bit equal to the A1 bit.
15. The method of claim 13 wherein step (b) further comprises if the X1 bit is not equivalent to the X0 bit and the X1 bit is not equivalent to the A0 bit, setting the A3 bit equal to the X1 bit, otherwise setting the A3 bit equal to the A2 bit.
16. The method of claim 13 wherein step (a) is executed in a first clock cycle and step (b) is executed in a second clock cycle.
17. The method of claim 13 wherein step (a) and step (b) are executed in parallel in the same clock cycle.
18. An apparatus for parallel calculation of prediction bits for a spatially predicted coded block pattern having an A0 bit, an A1 bit, an A2 bit, and an A3 bit, the apparatus comprising:
a storage device storing rows of bits including the spatially predicted coded block pattern, a D0 bit, an X0 bit, an X1 bit, a Y0 bit, and a Y1 bit;
a first circuit connected to the storage device for setting the A0 bit;
a second circuit connected to the storage device for setting the A2 bit;
wherein the first circuit and the second circuit operate in parallel; and
the storage device comprises a shift register and after a first clock cycle, the shift register is shifted and the first circuit and the second circuit are used for setting the A1 bit and the A3 bit respectively in a second clock cycle.
19. An apparatus for parallel calculation of prediction bits for a spatially predicted coded block pattern having an A0 bit, an A1 bit, an A2 bit, and an A3 bit, the apparatus comprising:
a storage device storing rows of bits including the spatially predicted coded block pattern, a D0 bit, an X0 bit, an X1 bit, a Y0 bit, and a Y1 bit;
a first circuit connected to the storage device for setting the A0 bit;
a second circuit connected to the storage device for setting the A2 bit;
wherein the first circuit and the second circuit operate in parallel;
the first circuit comprises:
a first comparator connected to the storage device for indicating when the D0 bit and the X0 bit are equivalent; and
a first multiplexer connected to the storage device for selectively setting the A0 bit equal to the X0 bit or the Y0 bit depending on the output of the first comparator; and
the second circuit comprises:
a second comparator connected to the storage device for indicating when the X0 bit and the Y0 bit are equivalent;
a first NOR-gate having inputs connected to the output of the first comparator and the output of the second comparator; and
a second multiplexer connected to the storage device for selectively setting the A2 bit equal to the Y1 bit or the X0 bit depending on the output of the first NOR-gate.
20. An apparatus for parallel calculation of prediction bits for a spatially predicted coded block pattern having an A0 bit, an A1 bit, an A2 bit, and an A3 bit, the apparatus comprising:
a storage device storing rows of bits including the spatially predicted coded block pattern, a D0 bit, an X0 bit, an X1 bit, a Y0 bit, and a Y1 bit;
a first circuit connected to the storage device for setting the A0 bit;
a second circuit connected to the storage device for setting the A2 bit;
a third circuit connected to the storage device for setting the A1 bit; and
a fourth circuit connected to the storage device for setting the A3 bit;
wherein the third circuit comprises:
a third comparator connected to the storage device for indicating when the X0 bit and the X1 bit are equivalent; and
a third multiplexer connected to the storage device for selectively setting the A1 bit equal to the X1 bit or the A0 bit depending on the output of the third comparator;
the fourth circuit comprises:
a fourth comparator connected to the storage device for indicating when the X1 bit and the A0 bit are equivalent;
a second NOR-gate having inputs connected to the output of the third comparator and the output of the fourth comparator; and
a fourth multiplexer connected to the storage device for selectively outputting the A2 bit or the X1 bit as the A3 bit depending on the output of the second NOR-gate; and
the first circuit, the second circuit, the third circuit, and the fourth circuit operate in parallel.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A compound of formula I:
or a prodrug, pharmaceutically acceptable salt, or solvate thereof.
2. The compound of claim 1 as a pharmaceutically acceptable salt thereof.
3. The compound of claim 2 wherein the pharmaceutically acceptable salt is a hydrochloride.
4. A method for treating a patient suffering from, or subject to, a physiological condition in need of amelioration of an inhibitor of tryptase comprising administering to the patient a therapeutically effective amount of the compound of claim 1.
5. The method of claim 4, wherein the physiological condition is selected from the group consisting of inflammatory disease, a disease of joint cartilage destruction, ocular conjunctivitis, vernal conjunctivitis, inflammatory bowel disease, asthma, allergic rhinitis, interstitial lung disease, fibrosis, sceleroderma, pulmonary fibrosis, liver cirrhosis, myocardial fibrosis, neurofibroma, hypertrophic scar, dermatological condition, condition related to atherosclerotic plaque rupture, periodontal disease, diabetic retinopathy, tumor growth, anaphylaxis, multiple sclerosis, peptic ulcer, and syncytial viral infection.
6. The method of claim 5, wherein the physiological condition is inflammatory disease.
7. The method of claim 6 wherein the inflammatory disease is joint inflammation, arthritis, rheumatoid arthritis, rheumatoid spondylitis, gouty arthritis, traumatic arthritis, rubella arthritis, psoriatic arthritis, or osteoarthritis.
8. The method of claim 5, wherein the physiological condition is COPD.
9. The method of claim 5, wherein the physiological condition is COPD exacerbations.
10. The method of claim 5, wherein the physiological condition is a dermatological condition.
11. The method of claim 10, wherein the dermatological condition is atopic dermatitis or psoriasis.
12. The method of claim 5, wherein the physiological condition is related to atherosclerotic plaque rupture.
13. The method of claim 12, wherein the atherosclerotic plaque rupture is consequent to myocardial infarction, stroke, or angina.
14. A method for treating a patient suffering from asthma, comprising administering to the patient a combination of a therapeutically effective amount of a compound of claim 1, and a second compound selected from the group consisting of a beta andrenergic agonist, anticholinergic, anti-inflammatory corticosteroid, and anti-inflammatory agent.
15. The method of claim 4, wherein the administering is such that the compound of claim 1 is preferentially distributed to lung tissue versus plasma.
16. A pharmaceutical composition comprising a therapeutically effective amount of a compound of claim 1 and a pharmaceutically acceptable carrier thereof.
17. A pharmaceutical composition comprising a compound of claim 1 and a therapeutically effective amount of a second compound selected from the group consisting of a beta andrenergic agonist, anticholinergic, anti-inflammatory corticosteroid, and anti-inflammatory agent; and a pharmaceutically acceptable carrier.
18. The pharmaceutical composition of claim 17, wherein the second compound is a beta andrenergic agonist.
19. The pharmaceutical composition of claim 18, wherein the beta andrenergic agonist is selected from albuterol, terbutaline, formoterol, fenoterol, or prenaline.
20. The pharmaceutical composition of claim 17, wherein the second compound is an anticholinergic.
21. The pharmaceutical composition of claim 20, wherein the anticholinergic is ipratropium bromide.
22. The pharmaceutical composition of claim 17, wherein the second compound is an anti-inflammatory corticosteroid.
23. The pharmaceutical composition of claim 22, wherein the anti-inflammatory corticosteroid is selected from beclomethasone dipropionate, triamcinolone acetonide, flunisolide or dexamethasone.
24. The pharmaceutical composition of claim 17, wherein the second compound is an anti-inflammatory agent.
25. The pharmaceutical composition of claim 24, wherein the anti-inflammatory agent is sodium cromoglycate or nedocromil sodium.
26. The pharmaceutical composition of claim 17, wherein the second compound is a pharmaceutically acceptable carrier thereof.