1. An armor repair kit comprising:
an armor repair putty comprising a resinous material;
one or more scrims having a plurality of ceramic constituents fixedly attached thereto;
and an elastomeric housing.
2. The armor repair kit of claim 1, wherein the armor repair putty further comprises a plurality of ceramic constituents.
3. The armor repair kit of claim 1, wherein the armor repair putty further comprises a plurality of reinforcement fibers.
4. The armor repair kit of claim 1, wherein the armor repair putty is partially pre-cured.
5. The armor repair kit of claim 1, further comprising a shock-absorbing material layer.
6. The armor repair kit of claim 1, further comprising a repair disk.
7. The armor repair kit of claim 1, further comprising a boundary frame, wherein the boundary frame comprises conformable material.
8. The armor repair kit of claim 1, further comprising a studded sub-frame and slotted sub-frame, wherein portions of the studded sub-frame and portions of the slotted sub-frame are capable of being joined together using a mechanical fastener.
9. The armor repair kit of claim 1, further comprising a handheld tool for mixing the armor repair putty.
10. The armor repair kit of claim 1, further comprising a handheld tool for applying the armor repair putty.
11. The armor repair kit of claim 1, further comprising a handheld tool for curing the armor repair putty.
12. A method for repairing armor comprising:
applying a first amount of an armor repair putty comprising a resinous material to a damaged area of armor;
applying an elastomeric housing containing one or more scrims having a plurality of ceramic constituents attached thereto and a second amount of armor repair putty over top of the first amount of the armor repair putty; and
curing the first and second amounts of the armor repair putty.
13. The method of claim 12, wherein the armor repair putty further comprises a plurality of ceramic constituents.
14. The method of claim 12, wherein the armor repair putty further comprises a plurality of reinforcement fibers.
15. The method of claim 12, wherein the armor repair putty is partially pre-cured.
16. The method of claim 12, further comprising the step of applying a shock-absorbing material layer to the damaged area of armor.
17. The method of claim 12, further comprising the step of applying a repair disk to the damaged area of armor.
18. The method of claim 12, further comprising the step of securing a boundary frame to a surface surrounding the damaged area of armor.
19. The method of claim 18, wherein the boundary frame comprises a conformable material.
20. The method of claim 12, wherein the elastomeric housing containing the one or more scrims having the plurality of ceramic constituents attached thereto and the second layer of armor repair putty is secured to the boundary frame by a mechanical fastener.
21. The method of claim 12, further comprising the step of cleaning the damaged area of annor.
22. A method for enhancing non-damaged armor comprising:
applying a layer of an armor repair putty comprising a resinous material to an area of armor;
applying one or more scrims having a plurality of ceramic constituents attached thereto;
filling the interstitial spaces between the plurality of ceramic constituents with the armor repair putty, and
curing the annor repair putty.
23. The method of claim 22, wherein the armor repair putty further comprises a plurality of ceramic constituents.
24. The method of claim 22, wherein the armor repair putty further comprises a plurality of reinforcement fibers.
25. The method of claim 22, wherein the armor repair putty is partially pre-cured.
26. The method of claim 22, further comprising the step of applying a shock-absorbing material layer.
27. The method of claim 22, further comprising the step of securing a boundary frame to a surface surrounding the area of armor.
28. The method of claim 27, wherein the boundary frame comprises a conformable material.
29. The method of claim 22, further comprising the step of cleaning the area of armor.
30. The method of claim 22, wherein the one or more scrims having the plurality of ceramic constituents attached thereto is contained in an elastomeric housing.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A semiconductor device comprising:
a plurality of interlayer insulating films stacked on a semiconductor substrate;
at least three or more wiring layers formed in the plurality of interlayer insulating films; and
a chip strength reinforcement formed in the plurality of interlayer insulating films, wherein
the chip strength reinforcement is made of a plurality of dummy wiring structures and
each of the plurality of dummy wiring structures is formed to extend across and within two or more of the wiring layers including only one or none of the bottommost wiring layer and the topmost wiring layer using a via portion.
2. The semiconductor device of claim 1, wherein
at least two of the plurality of dummy wiring structures have at least a portion formed in the same wiring layer.
3. The semiconductor device of claim 1, wherein
at least one of a pair of dummy wiring structures among the plurality of dummy wiring structures has a portion formed in one of the wiring layers in which the other of the pair is not formed.
4. The semiconductor device of claim 1, wherein
at least two of the plurality of dummy wiring structures have a portion formed in the bottommost wiring layer.
5. The semiconductor device of claim 1, wherein
at least one of the plurality of dummy wiring structures has a portion extending in a certain direction in at least one of the wiring layers and another portion extending in a different direction in the same wiring layer and being connected to the certain portion.
6. The semiconductor device of claim 1, wherein
the plurality of dummy wiring structures include a first dummy wiring structure and a second dummy wiring structure whose topmost portion is positioned below the topmost portion of the first dummy wiring structure,
at least two portions of the first dummy wiring structure are formed in at least two wiring layers, respectively, and at least two portions of the second dummy wiring structure are formed in the same at least two wiring layers, respectively, and
one of the at least two portions of the first dummy wiring structure formed in one of the at least two wiring layers and one of the at least two portions of the second dummy wiring structure formed in the other of the at least two wiring layers overlap each other when viewed in plan.
7. The semiconductor device of claim 6, wherein
the second dummy wiring structure is formed to extend across and within three or more wiring layers using via portions and configured in the form of a ring and
a portion of the first dummy wiring structure is positioned inside the ring-shaped second dummy wiring structure.
8. The semiconductor device of claim 7, wherein
the first dummy wiring structure is formed to extend across and within three or more wiring layers using via portions and configured in the form of a ring and
a portion of the second dummy wiring structure is positioned inside the ring-shaped first dummy wiring structure.
9. The semiconductor device of claim 1, wherein
each of the plurality of dummy wiring structures contains copper.
10. The semiconductor device of claim 1, wherein
the plurality of dummy wiring structures are provided at the corners of the chip region of the semiconductor substrate.
11. The semiconductor device of claim 1, wherein
at least one of the plurality of dummy wiring structures does not include the topmost wiring layer, and is formed to extend across and within two or more wiring layers including the bottommost wiring layer using a via portion.
12. The semiconductor device of claim 1, wherein
at least one of the plurality of dummy wiring structures does not include the bottommost wiring layer, and is formed to extend across and within two or more wiring layers including the topmost wiring layer using a via portion.
13. The semiconductor device of claim 1, wherein
at least one of the plurality of dummy wiring structures is formed to extend across and within two or more wiring layers including none of the topmost wiring layer and the bottommost wiring layer using a via portion.
14. The semiconductor device of claim 1, wherein
the interlayer insulating film includes an insulating film made of low dielectric constant material.
15. The semiconductor device of claim 1, wherein
the interlayer insulating film includes a silicon carbon nitride film.
16. The semiconductor device of claim 1, wherein
the interlayer insulating film includes a silicon carbon oxide film.
17. The semiconductor device of claim 1, wherein
the interlayer insulating film includes a carbon-containing silicon oxide film.