1. An optical network system comprising:
a first network element, the first network element having a stack associated with a first protocol, the first network element being arranged to send a signal including at least one DCC channel, the DCC channel being arranged to contain information;
a second network element, the second network element having a stack associated with a second protocol, the second network element being arranged to receive the signal including the at least one DCC channel, the second network element further being arranged to extract the information from the DCC channel and to send the extracted information from the DCC channel; and
an external router, the external router being contained within a first portion of the network system, the external router being arranged to cooperate with the second network element to support a point-to-point-over-Ethernet session, the external router being arranged to receive the extracted information from the DCC channel and to forward the extracted information from the DCC channel through the first portion of the network system.
2. The optical network system of claim 1 wherein the second network element is a gateway network element, and the external router is located at a point of entry into the first portion of the network.
3. The optical network system of claim 1 wherein the first portion of the network is a customer network, and the first network element and the second network element are not located in the customer network.
4. The optical network system of claim 1 wherein the first protocol is an OSI protocol.
5. The optical network system of claim 4 wherein the second protocol is an IP protocol.
6. The optical network system of claim 1 wherein the second network element is a gateway network element.
7. The optical network system of claim 1 wherein the information is management information, the management information being encapsulated in a link access protocol on a D channel (LAPD) message contained in the DCC channel.
8. The optical network system of claim 7 wherein when the second network element extracts the information and sends the extracted information, the second network element terminates the DCC channel.
9. A gateway network element comprising:
a first port, the first port being arranged to receive a message from a network element having a stack associated with a first protocol, wherein the message includes information contained in a DCC channel;
a retrieving mechanism, the retrieving mechanism being arranged to extract the information contained in the DCC channel;
a second port, the second port being arranged to support a point-to-point-over-Ethernet (PPPOE) session with an external router; and
a sending mechanism, the sending mechanism being arranged to send the extracted information using the second port, wherein the extracted information is sent using a second protocol.
10. The gateway network element of claim 9 further including:
a terminating mechanism, the terminating mechanism being arranged to terminate the DCC channel.
11. The gateway network element of claim 9 wherein the first protocol is an OSI protocol and the second protocol is an IP-based protocol.
12. The gateway network element of claim 9 wherein the first port is an optical port and the second port is an Ethernet port.
13. The gateway network element of claim 9 wherein the first port is associated with a point-to-point connection.
14. A gateway network element comprising:
a first port, the first port being arranged to receive a message from a network element having a stack associated with a first protocol, wherein the message includes information contained in a DCC channel; code devices that cause information contained in the DCC channel to be extracted;
a second port, the second port being arranged to support a point-to-point-over-Ethernet (PPPOE) session with an external router;
code devices that cause the extracted information to be sent using the second port, wherein the extracted information is sent using a second protocol; and
a memory that stores the code devices.
15. The gateway network element of claim 14 further including:
code devices that cause the DCC channel to be terminated.
16. The gateway network element of claim 14 wherein the first protocol is an OSI protocol and the second protocol is an IP-based protocol.
17. The gateway network element of claim 14 wherein the first port is an optical port and the second port is an Ethernet port.
18. The gateway network element of claim 14 wherein the first port is associated with a point-to-point connection.
19. A gateway network element comprising:
a first port, the first port being arranged to receive a message from a network element having a stack associated with a first protocol, wherein the message includes information contained in a DCC channel;
means for extracting the information contained in the DCC channel;
a second port, the second port being arranged to support a point-to-point-over-Ethernet (PPPOE) session with an external router; and
means for sending the extracted information using the second port, wherein the extracted information is sent using a second protocol.
20. The gateway network element of claim 19 further including:
means for terminating the DCC channel.
21. The gateway network element of claim 19 wherein the first protocol is an OSI protocol and the second protocol is an IP-based protocol.
22. A router, the router being arranged to receive a signal with an OSI message within which a DCC channel has been terminated from a network element, the router comprising:
a port, the port being arranged to engage in a point-to-point-over-Ethernet (PPPoE) session during which the signal with the OSI message within which the DCC channel has been terminated is received; and
a message processor, the message processor being arranged to process the OSI message within which the DCC channel has been terminated.
23. The router of claim 22 wherein the message processor is further arranged to terminate portions of the signal.
24. The router of claim 22 further including:
a provisioner, the provisioner being arranged to provision the router to receive the OSI message.
25. The router of claim 22 wherein the network element is a network element without an OSI stack, and the port is arranged to receive the signal with the OSI message within which the DCC channel has been terminated from the network element without the OSI stack.
26. A router, the router being arranged to receive a signal with an OSI message within which a DCC channel has been terminated from a network element, the router comprising:
means for engaging in a point-to-point-over-Ethernet (PPPoE) session during which the signal with the OSI message within which the DCC channel has been terminated is received; and
means for processing the OSI message within which the DCC channel has been terminated.
27. The router of claim 26 further including means for terminating portions of the signal.
28. The router of claim 26 further including:
means for provisioning the router to receive the OSI message.
29. A router, the router being arranged to receive a signal with an OSI message within which a DCC channel has been terminated from a network element, the router comprising:
code devices that cause a point-to-point-over-Ethernet (PPPOE) session to be initiated during which the signal with the OSI message within which the DCC channel has been terminated is received; and
code devices that cause the OSI message within which the DCC channel has been terminated.
30. The router of claim 29 further including code devices that cause portions of the signal to be terminated.
31. The router of claim 29 further including:
code devices that cause the router to provisioned to receive the OSI message.
32. A method for processing an optical signal received from an optical network element with an OSI stack, the method comprising:
receiving the signal, the signal including a DCC channel which contains an encapsulated message, the encapsulated message including information;
extracting the information from the encapsulated message; and
sending the information using a point-to-point-over-Ethernet (PPPoE) session.
33. The method of claim 32 wherein the encapsulated message is a link access protocol on a D channel (LAPD) encapsulated message, the method further including:
terminating the LAPD; and
sending the signal without the LAPD using the PPPoE session.
34. The method of claim 33 wherein terminating the LAPD includes terminating the DCC channel.
35. The method of claim 32 wherein the information is management information
wherein the signal is received on a point-to-point connection associated with an optical port.
36. The method of claim 32 wherein sending the information using the point-to-point-over-Ethernet (PPPoE) session includes passing the information to a PPPoE stack for forwarding.
37. A method for processing a signal received from an optical network element without an OSI stack, the signal including an OSI message with a terminated DCC channel, the method comprising:
provisioning a port for a point-to-point-over-Ethernet (PPPoe) session to receive the OSI message;
receiving the OSI message; and
processing the OSI message.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A semiconductor memory device comprising:
a substantially planar substrate;
a memory string disposed substantially vertical to the substrate, the memory string comprising a plurality of storage cells; and
a plurality of word lines, each word line including a first portion disposed substantially parallel to the substrate and connected to the memory string and a second portion disposed substantially inclined relative to the substrate,
wherein a first group of the plurality of word lines are electrically connected to first conductive lines disposed at a first side of the memory string, and a second group of the plurality of word lines are electrically connected to second conductive lines disposed at a second side of the memory string.
2. The device of claim 1 wherein a word line of the first group of word lines and a word line of the second group of word lines are alternately positioned between each other in the direction extending from top to bottom of the memory string.
3. The device of claim 1 wherein the inclination of the elongated memory string is substantially 90 degrees relative to the planar substrate and the first side of the memory string is disposed opposite to the second side of the memory string.
4. The device of claim 1 wherein the first portions of each of the plurality of word lines are parallel to each other, respectively.
5. The device of claim 4 wherein the second portions of each of the plurality of word lines at the first side of the memory string are parallel to each other, respectively, and the second portions of each of the plurality of word lines at the second side of the memory string are parallel to each other, respectively.
6. The device of claim 1 wherein the first alternating word lines are disposed on odd numbered storage cells counting from top to bottom of the memory string, respectively, and the second alternating word lines are disposed on even numbered storage cells counting from top to bottom of the memory string, respectively.
7. The device of claim 6, further comprising insulating caps disposed at the elevated ends of the second portions of even numbered word lines at the first side of the memory string, and at the elevated ends of the second portions of odd numbered word lines at the second side of the memory string.
8. The device of claim 6, further comprising at least two row decoders, one row decoder disposed on the side of the odd numbered storage cells and another row decoder disposed on the side of the even numbered storage cells.
9. The device of claim 8 wherein a first row decoder of the two is connected to either even or odd string select lines (SSLs) and even word lines, and a second row decoder of the two is connected to either odd or even SSLs and odd word lines, respectively.
10. The device of claim 8 wherein a first row decoder of the two is connected to all of the string select lines (SSLs) and either even or odd word lines, and a second row decoder of the two is connected to either odd or even word lines, respectively.
11. The device of claim 1, further comprising a third group of word lines connected to a third conductive line disposed on a third side of the memory string, wherein the first group of word lines connect to modulus three remainder one numbered storage cells counting from top to bottom of the memory string, respectively, the second group of word lines connect to modulus three remainder two numbered storage cells counting from top to bottom of the memory string, respectively, and the third group of word lines connect to modulus three remainder zero numbered storage cells counting from top to bottom of the memory string, respectively.
12. The device of claim 1 wherein each of the plurality of storage cells and corresponding word lines occupies a different plane disposed parallel to the plane of the substrate.
13. The device of claim 12 wherein contiguous portions of a word line disposed in the same plane on different sides of the memory string are electrically connected as one word line.
14. The device of claim 1 wherein the substrate is horizontal and the memory string is vertical, the device further comprising a peripheral area disposed above the planar substrate.
15. The device of claim 1, further comprising a plurality of conductive patterns for contact pads disposed between the first alternating word lines of the plurality of word lines and the first conductive lines, and between the second alternating word lines of the plurality of word lines and the second conductive lines.
16. The device of claim 15, further comprising a peripheral area disposed above the planar substrate.
17. The device of claim 16 wherein the peripheral area is disposed in the same level as the lower surface of conductive patterns.
18. The device of claim 1 wherein the inclined second portions of the word lines are disposed at an inclination angle between about 50 and about 90 degrees relative to the substrate.
19. The device of claim 1 wherein inclined second portions extend from both ends of the first portion of each word line, and one of each pair of inclined second portions from each word line is terminated with an insulating cap.
20. The device of claim 1, further comprising a plurality of bit lines disposed substantially perpendicular to each of the memory string and the word lines.
21. The device of claim 1 further comprising a chamber disposed on the planar substrate wherein the chamber comprises a silicon (Si) recess in the substrate, and the elongated memory string and elongated word lines are disposed in the Si recess.
22. The device of claim 1 further comprising a chamber disposed on the planar substrate wherein the chamber comprises an insulating wall disposed on top of the substrate, and the elongated memory string and elongated word lines are disposed within the periphery of the insulating wall.
23. The device of claim 1 wherein the elongated word lines comprise metal or silicide.
24. The device of claim 1 wherein the memory string comprising the plurality of storage cells is substantially columnar, tubular, or bar-sided.
25. The device of claim 1 wherein the substrate comprises silicon, the insulating layers comprise silicon oxide, and the word lines comprise metal.
26. The device of claim 1 wherein the storage cell comprises a control gate, a first insulating region, a charge storage region, and a second insulating region.
27. The device of claim 1 wherein the storage cell comprises a metal gate as a control gate, a high-K region as a blocking layer, a nitride region as a charge storage layer, and an oxide region as a tunnel layer.
28. A method of forming a semiconductor memory device, the method comprising:
providing a substrate;
forming a chamber on the substrate;
depositing a plurality of alternating insulating layers and sacrificial layers in the chamber, each layer having a horizontal first portion and at least one inclined second portion;
forming a hole substantially normal to the substrate and extending through the layers to the substrate;
depositing a vertically inclined memory string into the hole, the memory string comprising a plurality of storage cells;
replacing the sacrificial layers with conductive layers to form a plurality of elongated word lines, respectively; and
connecting first alternating word lines of the plurality to conductive lines disposed at a first side of the memory string, and second alternating word lines of the plurality to conductive lines disposed at a second side of the memory string.
29. The method of claim 28, further comprising forming a peripheral area on a surface at the top level of the memory string.
30. The method of claim 28 wherein the vertical memory string is bar-sided, the method further comprising forming a trench for x-cut to divide the memory string into two parallel strings.
31. The method of claim 28 wherein the substrate comprises silicon, the insulating layers comprise silicon oxide, and the word lines comprise metal.
32. The method of claim 28 wherein the chamber is recessed directly into the substrate.
33. The method of claim 28 wherein the chamber is formed on top of the substrate by forming insulating sidewalls thereon.
34. The method of claim 28 wherein each storage cell comprises a control gate, a first insulating region, a charge storage region, and a second insulating region.
35. The method of claim 28 wherein each storage cell comprises a metal gate as a control gate, a high-K region as a blocking layer, a nitride region as a charge storage layer, and an oxide region as a tunnel layer.
36. A semiconductor memory device comprising:
a substrate;
a memory string disposed on and substantially normal to the substrate, the memory string comprising a plurality of storage cells; and
a plurality of word lines, each word line including a first portion substantially parallel to the substrate and coupled to the memory string and a second portion substantially inclined relative to the substrate and extending upwardly,
wherein first alternating word lines of the plurality of word lines are electrically connected to first conductive lines disposed at a first side of the memory string, and second alternating word lines of the plurality of word lines are electrically connected to second conductive lines disposed at a second side of the memory string.
37. A semiconductor memory device comprising:
a substrate;
a memory string disposed on and substantially normal to the substrate, the memory string comprising a plurality of storage cells; and
a plurality of word lines, each word line including a first portion substantially parallel to the substrate and coupled to the memory string and a second portion substantially inclined relative to the substrate and extending upwardly,
wherein the word lines comprise first word lines selectively connected to first conductive lines disposed at a first side of the memory string, and second word lines selectively connected to second conductive lines disposed at a second side of the memory string.
38. The device of claim 37, wherein the word lines comprise at least one dummy word line.
39. The device of claim 37, wherein the first side has a first row decoder and the second side has a second row decoder.
40. A semiconductor memory device comprising:
a substrate;
a memory string disposed on and substantially normal to the substrate, the memory string comprising a plurality of storage cells;
a plurality of word lines; and
at least two row decoders,
wherein the plurality of word lines includes a first group of word lines electrically connected to one row decoder at a first side of the memory string and a second group of word lines electrically connected to the other row decoder at a second side of the memory string.
41. The device of claim 40 wherein the first row decoder is connected to one group of string select lines (SSLs) at a first side of the memory string, and the second row decoder is connected to another group of SSLs at a second side of the memory string.
42. The device of claim 40 wherein either one of the two row decoders is connected to all of the string select lines (SSLs).
43. The device of claim 40, wherein each of the word lines includes a first portion disposed substantially parallel to the substrate and connected to the memory string and a second portion disposed substantially inclined relative to the substrate.
44. The device of claim 40, wherein the memory string is configured to make a current path substantially vertical to the substrate.
45. A method of forming a semiconductor memory device, the method comprising:
providing a substrate;
forming a chamber on the substrate;
depositing a plurality of alternating insulating layers and conductive layers in the chamber, the conductive layers forming a plurality of word lines, each layer having a horizontal first portion and at least one inclined second portion;
forming a hole substantially normal to the substrate and extending through the layers to the substrate;
depositing a vertically inclined memory string into the hole, the memory string comprising a plurality of storage cells; and
connecting first alternating word lines of the plurality of word lines to contact pads disposed at a first side of the memory string, and second alternating word lines of the plurality of word lines to contact pads disposed at a second side of the memory string.