1. A two stage analog amplifier circuit, comprising:
a first stage having an input device that receives an input signal at a first input gate, the first input gate having a thick gate oxide layer wherein the thickness of the thick gate oxide layer is chosen so that the first stage input device has a low input gate leakage current, the first stage producing a first stage output signal; and
a second stage having a second input device that receives the first stage output signal at a second input gate, the second input gate having a thin gate oxide layer wherein the thickness of the thin gate oxide layer is less than the thickness of the thick gate oxide layer of the first input gate, wherein the first stage is a wideband amplifier having a first stage gain that is limited to enhance the first stage frequency response, wherein the second stage has a second stage gain that is greater than the first stage gain and the second stage gain is limited to enhance the second stage frequency response, and wherein the combined first stage gain and second stage gain meet a required system gain that is a product of the first stage gain and the second stage gain.
2. The two stage analog amplifier circuit of claim 1 wherein the first stage has a gain that is greater than 1.
3. The two stage analog amplifier circuit of claim 1 wherein the thin gate oxide layer is about \u2154 the thickness of the gate oxide layer of the first stage input device.
4. The two stage analog circuit of claim 1 wherein the input device and the second stage input device are MOSFET transistors where the thickness of the MOSFET transistor’s gate oxide layer decreases with increasing transistor gate leakage current density.
5. The two stage analog amplifier circuit of claim 1 wherein the two stage circuit is an operational amplifier whose first stage input is connected to a hold capacitor in a sample and hold circuit.
6. The two stage analog amplifier circuit of claim 1 wherein the two stage analog amplifier circuit is used in a read channel of a disk drive system.
7. The two stage analog amplifier circuit of claim 1 further comprises:
the first stage having a third input device that receives a second input signal at a third input gate, the third input gate having a thick oxide layer wherein the thickness of the thick gate oxide layer is chosen so that the third input device has a low input gate leakage current, the first stage producing a first stage second output signal in response to the second input signal; and
the second stage having a fourth input device that receives the first stage second output signal at a fourth input gate, the fourth input gate having a thin gate oxide layer wherein the thickness of the thin gate oxide layer is less than the thickness of the thick gate oxide layer of the third input gate.
8. A two stage analog amplifier circuit, comprising:
a first stage having an input device that receives an input signal at a first input gate, the first input gate having a thick gate oxide layer wherein the thickness of the thick gate oxide layer is chosen so that the first stage input device has a low input gate leakage current, the first stage producing a first stage output signal;
a second stage having a second input device that receives the first stage output signal at a second input gate, the second input gate having a thin gate oxide layer wherein the thickness of the thin gate oxide layer is less than the thickness of the thick gate oxide layer of the first input gate;
two first stage input devices used as differential inputs in a first stage of a two stage differential variable gain amplifier (VGA) circuit; and
two second stage input devices used as differential inputs in a second stage of the two stage differential VGA circuit, whereby the two stage differential VGA circuit is used in a read channel of a disk drive system.
9. The two stage analog amplifier circuit of claim 8 wherein the read channel reads media recorded with a perpendicular recording technology.
10. The two stage analog amplifier circuit of claim 8 wherein the first stage is a wideband amplifier having a first stage gain that is limited to enhance the first stage frequency response, the second stage has a second stage gain that is greater than the first stage gain and the second stage gain is limited to enhance the second stage frequency response, and wherein the combined first stage gain and second stage gain meet a required system gain that is a product of the first stage gain and the second stage gain.
11. A two stage differential amplifier circuit for a read channel, comprising:
a first stage having differential input devices with input gates receiving a differential input signal, the input gates each having a thick gate oxide layer, wherein each of the differential input devices has a low input gate leakage current, the first stage having a common mode voltage (CMV) output, the first stage using a common mode signal to provide stable control over the common mode voltage output, the first stage producing a differential output signal; and
a second stage having second differential input devices with second input gates receiving the differential output signal of the first stage, the second input gates each having a thin gate oxide wherein the thicknesses of the thin gate oxide layer is less than the thickness of the thick gate oxide layer of the first stage differential input devices, wherein the first stage is a wideband amplifier having a first stage gain that is limited to enhance the first stage frequency response, the second stage has a second stage gain that is greater than the first stage gain and the second stage gain is limited to enhance the second stage frequency response, and wherein the combined first stage gain and second stage gain meet a required system gain that is a product of the first stage gain and the second stage gain.
12. The two stage differential amplifier circuit of claim 11 wherein the common mode signal is a common mode feedforward signal used to control the first stage common mode voltage output by current mirroring whereby the first stage common mode voltage output is matched to an external target common mode voltage input.
13. The two stage differential amplifier circuit of claim 11 wherein the common mode signal is a common mode feedback (CMFB) signal based on sensing the common mode voltage (CMV) output of the first stage and using the CMFB signal to control the CMV output of the first stage to match a target common mode voltage input.
14. The two stage differential amplifier circuit of claim 11 further comprising:
a resistor connected to a voltage source;
an amplifier with a negative input connected to a second terminal of the resistor, a positive input connected to a common mode voltage target value, and an output;
a first control device having an input gate connected to the amplifier output, a source node connected to the second terminal of the resistor, and a drain node;
a second control device having an input gate connected to the drain of the first control device, a drain connected to the drain of the first control device, and a source connected to a reference voltage; and
an input controlling device having an input gate connected to the input gate of the second controlling device, a source connected to a reference voltage, and a drain connected to the sources of both differential input devices, whereby the current through the second control device is mirrored into the input controlling device by device matching and whereby the circuit’s CMV output is set.
15. The two stage differential amplifier circuit of claim 11 further comprising:
a first resistor;
a second resistor, the second resistor matched in value to the first resistor, the first resistor connected to the second resistor constituting a first node, the first resistor connected to the drain of one of the differential input thick oxide devices, and the second resistor connected to the drain of the other differential input thick oxide device;
an input controlling device having an input gate, a source connected to a reference voltage, and a drain connected to the sources of both differential input devices; and
an amplifier positive input connected to the first node, the amplifier negative input connected to a common mode voltage target value, and the amplifier output connected to the input gate of the input controlling device, whereby the input controlling device controls the voltage of the first node to match the common mode voltage target value.
16. A method for amplifying a read channel signal with a system gain, system frequency response, and low input gate leakage current, comprising:
receiving a read channel signal in a first stage circuit having a low input gate leakage current depending on the thickness of the first stage input gate oxide layer;
amplifying the received read channel signal by a first gain and first frequency response of at least the system frequency response;
providing the amplified read channel signal on a first stage output;
receiving the first stage output signal in a second stage circuit having a second frequency response and a second gain depending on the thickness of the second stage input gate oxide layer, wherein the thickness of the second stage input gate oxide layer is less than the thickness of the first stage input gate oxide layer,
amplifying the received first stage output signal by the second gain and second frequency response of at least the system frequency response, wherein the second gain is greater than the first gain; and
providing the amplified read channel signal on a second stage output, wherein the read channel signal is amplified by the system gain that is a product of the first gain and the second gain.
17. The method of claim 16 wherein the thick gate oxide layer of the first stage circuit input gate is about 1.5 times the thickness of the gate oxide layer of the second stage circuit input gate.
18. The method of claim 16 wherein the read channel signal is sourced from a read transducer in a perpendicular recording technology.
19. The method of claim 16 further comprising:
sensing a common mode voltage of the first stage circuit;
comparing the common mode voltage of the first stage circuit with a reference common mode voltage in a differential amplifier;
adjusting the first stage circuit’s common mode voltage based on the output of the differential amplifier.
20. The method of claim 16 further comprising:
measuring a voltage comparable to a first stage common mode voltage in a separate feedforward common mode voltage circuit;
comparing the measured voltage with a reference common mode voltage in a differential amplifier; and
adjusting the first stage circuit’s common mode voltage based on the output of the differential amplifier.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A method of estimating routing congestion between pins in a net of an integrated circuit design using a computer system, comprising:
establishing one or more potential routes between the pins which pass through one or more buckets in the net, each bucket having a set of wiring tracks;
assigning a probabilistic usage to each bucket based on any partial blockage of the wiring tracks in each bucket, wherein said assigning includes creating a temporary usage map of the net buckets with an initial value of zero usage in every temporary usage map bucket, storing usage values in corresponding buckets of the temporary usage map, and deriving a final usage map from the temporary usage map;
computing routing congestion for each bucket using its probabilistic usage; and
storing the routing congestion for each bucket in said computer system.
2. The method of claim 1 wherein the net is a two-pin net that is a part of a larger multi-pin net, and further comprising constructing a tree to bridge the two-pin net to another pin of the multi-pin net.
3. The method of claim 1 wherein the routing congestion for each bucket is computed as a ratio of the bucket usage to bucket capacity.
4. The method of claim 1 wherein the routes are L-shaped having at least one bend in a bucket, and the probabilistic usage is proportional to a scale factor \u03b1 which is a ratio of a minimum number of available wiring tracks for a given route to a sum of minimum numbers of available wiring tracks for all possible routes.
5. The method of claim 1 wherein the routes are Z-shaped having at least two bends in two respective buckets, and the probabilistic usage is equal to a ratio of a minimum capacity of a given route to a sum of minimum capacities of all routes having an associated orientation with the given route.
6. The method of claim 5 wherein the minimum capacity F(n) of the given route n is
F(n)=min{F(u1)\xb7F(dn)FR(d1), . . . , F(un)\xb7F(dn)FR(dn), F(dn), F(en)\xb7F(dn)FL(dn), . . . , F(eQ)\xb7F(dQ)FL(dQ)},
where Q is the number of potential routes, d is one of a plurality of central span portions of the potential routes, u is one of a first plurality of edge portions of the potential routes that lie on a first side of the central span portions, e is one of a second plurality of edge portions of the potential routes that lie on a second side of the central span portions, F(un) is the capacity associated with edge un, F(dn) is the capacity associated with edge dn, F(en) is the capacity associated with edge en, FL(dn) is the total capacities of all central spans d to the left of span dn having an associated orientation with the given route, and FR(dn) is the total capacities of all central spans d to the right of span dn having the associated orientation with the given route.
7. A computer system comprising:
one or more processors which process program instructions;
a memory device connected to said processing means; and
program instructions residing in said memory device for estimating routing congestion between pins in a net of an integrated circuit design by establishing one or more potential routes between the pins which pass through one or more buckets in the net, each bucket having a set of wiring tracks, assigning a probabilistic usage to each bucket based on any partial blockage of the wiring tracks in each bucket wherein said assigning includes creating a temporary usage map of the net buckets with an initial value of zero usage in every temporary usage map bucket, storing usage values in corresponding buckets of the temporary usage map, and deriving a final usage map from the temporary usage map, and computing routing congestion for each bucket using its probabilistic usage.
8. The computer system of claim 7 wherein the net is a two-pin net that is a part of a larger multi-pin net, and said program instructions further construct a tree to bridge the two-pin net to another pin of the multi-pin net.
9. The computer system of claim 7 wherein the routing congestion for each bucket is computed as a ratio of the bucket usage to bucket capacity.
10. The computer system of claim 7 wherein the routes are L-shaped having at least one bend in a bucket, and the probabilistic usage is proportional to a scale factor \u03b1 which is a ratio of a minimum number of available wiring tracks for a given route to a sum of minimum numbers of available wiring tracks for all possible routes.
11. The computer system of claim 7 wherein the routes are Z-shaped having at least two bends in two respective buckets, and the probabilistic usage is equal to a ratio of a minimum capacity of a given route to a sum of minimum capacities of all routes having an associated orientation with the given route.
12. The computer system of claim 11 wherein the minimum capacity F(n) of the given route n is
F(n)=min{F(u1)\xb7F(dn)FR(d1), . . . , F(un)\xb7F(dn)FR(dn), F(dn), F(en)\xb7F(dn)FL(dn), . . . , F(eQ)\xb7F(dQ)FL(dQ)},
where Q is the number of potential routes, d is one of a plurality of central span portions of the potential routes, u is one of a first plurality of edge portions of the potential routes that lie on a first side of the central span portions, e is one of a second plurality of edge portions of the potential routes that lie on a second side of the central span portions, F(un) is the capacity associated with edge un, F(dn) is the capacity associated with edge dn, F(en) is the capacity associated with edge en, FL(dn) is the total capacities of all central spans d to the left of span dn having an associated orientation with the given route, and FR(dn) is the total capacities of all central spans d to the right of span dn having the associated orientation with the given route.
13. A computer program product comprising:
a computer-readable medium; and
program instructions residing in said medium for estimating routing congestion between pins in a net of an integrated circuit design by establishing one or more potential routes between the pins which pass through one or more buckets in the net, each bucket having a set of wiring tracks, assigning a probabilistic usage to each bucket based on any partial blockage of the wiring tracks in each bucket wherein said assigning includes creating a temporary usage map of the net buckets with an initial value of zero usage in every temporary usage map bucket, storing usage values in corresponding buckets of the temporary usage map, and deriving a final usage map from the temporary usage map, and computing routing congestion for each bucket using its probabilistic usage.
14. The computer program product of claim 13 wherein the net is a two-pin net that is a part of a larger multi-pin net, and said program instructions further construct a tree to bridge the two-pin net to another pin of the multi-pin net.
15. The computer program product of claim 13 wherein the routing congestion for each bucket is computed as a ratio of the bucket usage to bucket capacity.
16. The computer program product of claim 13 wherein the routes are L-shaped having at least one bend in a bucket, and the probabilistic usage is proportional to a scale factor \u03b1 which is a ratio of a minimum number of available wiring tracks for a given route to a sum of minimum numbers of available wiring tracks for all possible routes.
17. The computer program product of claim 13 wherein the routes are Z-shaped having at least two bends in two respective buckets, and the probabilistic usage is equal to a ratio of a minimum capacity of a given route to a sum of minimum capacities of all routes having an associated orientation with the given route.
18. The computer program product of claim 17 wherein the minimum capacity F(n) of the given route n is
F(n)=min{F(u1)\xb7F(dn)FR(d1), . . . , F(un)\xb7F(dn)FR(dn), F(dn), F(en)\xb7F(dn)FL(dn), . . . , F(eQ)\xb7F(dQ)FL(dQ)},
where Q is the number of potential routes, d is one of a plurality of central span portions of the potential routes, u is one of a first plurality of edge portions of the potential routes that lie on a first side of the central span portions, e is one of a second plurality of edge portions of the potential routes that lie on a second side of the central span portions, F(un) is the capacity associated with edge un, F(dn) is the capacity associated with edge dn, F(en) is the capacity associated with edge en, FL(dn) is the total capacities of all central spans d to the left of span dn having an associated orientation with the given route, and FR(dn) is the total capacities of all central spans d to the right of span dn having the associated orientation with the given route.