1. A re-writable memory, comprising:
a substrate;
a two-terminal cross point memory array formed above the substrate and including:
a first conductive array line;
second conductive array lines, each of the second conductive array lines oriented generally substantially perpendicular to the first conductive array line;
two-terminal memory plugs, each memory plug having a first terminal in electrical communication with the first conductive array line and a second terminal in electrical communication with one of the second conductive array lines, and each memory plug configured to assume a first electrical resistance that corresponds to a first data state in response to a first voltage and a second electrical resistance that corresponds to a second data state in response to a second voltage;
driver circuits, each driver circuit in electrical communication with the cross point array and operable to deliver the first voltage during a first cycle to a first group of memory plugs, and the second voltage during a second cycle following the first cycle, the second voltage delivered to a second group of memory plugs, the second group of memory plugs not including any memory plugs from the first group of memory plugs; and
address circuits in electrical communication with the driver circuits and configured to receive binary information and an address signal, the address circuits further configured to distribute the binary information to decoder circuits according to the address signal, so as to facilitate writing of the received binary information to the two-terminal memory plugs in page mode.
2. The re-writable memory of claim 1 and further comprising:
a data bus having a plurality of data lines, each data line in electrical communication with an associated one of the driver circuits, and each configured to pass information to the associated driver circuit for storage in the cross point memory array so as to collectively facilitate the writing of a set of binary information to the cross point memory array.
3. The re-writable memory of claim 1 and further comprising:
sensing circuits, each sensing circuit in electrical communication with one of the second conductive array lines and an associated one of the memory plugs, each sensing circuit further configured to sense an electrical current passing through said one of the second conductive array lines so as to read the first and second data states from the associated one of the memory plugs, and wherein the sensing circuits are configured to translate the first and second data states into binary information and wherein the sensing circuits are configured to output the binary information in page mode.
4. A re-writable memory, comprising:
a substrate;
a two-terminal cross point memory array formed above the substrate and including:
a first conductive array line;
second conductive array lines, each of the second conductive array lines oriented generally substantially perpendicular to the first conductive array line;
two-terminal memory plugs, each memory plug having a first terminal in electrical communication with the first conductive array line and a second terminal in electrical communication with one of the second conductive array lines, and each memory plug configured to assume a first electrical resistance that corresponds to a first data state in response to a first voltage and a second electrical resistance that corresponds to a second data state in response to a second voltage;
driver circuits, each driver circuit in electrical communication with the cross point array and operable to deliver the first voltage during a first cycle to a first group of memory plugs, and the second voltage during a second cycle following the first cycle, the second voltage delivered to a second group of memory plugs, the second group of memory plugs not including any memory plugs from the first group of memory plugs; and
a burst clock in electrical communication with the driver circuits and configured to trigger the driver circuits to write binary information to the two-terminal memory plugs in burst mode.
5. The re-writable memory of claim 4 and further comprising:
a data bus having a plurality of data lines, each data line in electrical communication with an associated one of the driver circuits, and each configured to pass information to the associated driver circuit for storage in the cross point memory array so as to collectively facilitate the writing of a set of binary information to the cross point memory array.
6. The re-writable memory of claim 4 and further comprising:
sensing circuits, each sensing circuit in electrical communication with one of the second conductive array lines and an associated one of the memory plugs, each sensing circuit further configured to sense an electrical current passing through said one of the second conductive array lines so as to read the first and second data states from the associated one of the memory plugs, and wherein the sensing circuits are configured to translate the first and second data states into binary information and wherein the sensing circuits are configured to output the binary information in burst mode.
7. A re-writable memory, comprising:
a substrate; and
a two-terminal cross point memory array formed above the substrate and including:
first conductive array lines;
second conductive array lines, each of the second conductive array lines oriented generally substantially perpendicular to the first conductive array lines;
two-terminal memory plugs, each memory plug having a first terminal in electrical communication with one of the first conductive array lines and a second terminal in electrical communication with one of the second conductive array lines, the memory plugs configured to store information in a first data state and a second data state;
driver circuits, each driver circuit in electrical communication with the cross point array and operable to program the first data state in a first portion of the two-terminal memory plugs during a first cycle, and the second data state in a second portion of the two-terminal memory plugs during a second cycle that follows the first cycle, the first portion and the second portion being mutually exclusive portions; and
address bits configured to identify selective ones of the driver circuits for input of said information in page mode.
8. A re-writable memory, comprising:
a substrate; and
a two-terminal cross point memory array formed above the substrate and including:
first conductive array lines;
second conductive array lines, each of the second conductive array lines oriented generally substantially perpendicular to the first conductive array lines;
two-terminal memory plugs, each memory plug having a first terminal in electrical communication with one of the first conductive array lines and a second terminal in electrical communication with one of the second conductive array lines, the memory plugs configured to store information in a first data state and a second data state;
driver circuits, each driver circuit in electrical communication with the cross point array and operable to program the first data state in a first portion of the two-terminal memory plugs during a first cycle, and the second data state in a second portion of the two-terminal memory plugs during a second cycle that follows the first cycle, the first portion and the second portion being mutually exclusive portions; and
a burst clock configured to sequentially trigger said driver circuits to input said information in burst mode.
9. A re-writable memory, comprising:
a substrate;
a two-terminal cross point memory array formed above the substrate and including:
a first conductive array line oriented generally in an x-direction;
second conductive array lines, each of the second conductive array lines oriented generally in a y-direction substantially perpendicular to the x-direction;
two-terminal memory plugs, each memory plug having a first terminal in electrical communication with one of the first conductive array lines and a second terminal in electrical communication with one of the second conductive array lines, each memory plug configured to store information in a first data state and a second data state so as to collectively store elements of an information set;
a plurality of driver circuits, each driver circuit in electrical communication with the cross point array, the plurality of driver circuits operable to substantially simultaneously program multiple ones of the memory plugs to either the first data state or the second data state, wherein the plurality of driver circuits is further configured to program the first data state to a first portion of the memory plugs during a first cycle and the second data state to a second portion of the memory plugs during a second cycle that follows the first cycle, wherein the first portion and the second portion being mutually exclusive portions; and
decoder circuits in electrical communication with a plurality of sensing circuits, the decoder circuits configured to determine from an address signal an order in which to enter the information set to a page register, so as to write the information in page mode.
10. The re-writable memory of claim 9 and further comprising:
a data bus in electrical communication with the plurality of driver circuits, the data bus configured to transmit digital information to the plurality of driver circuits so as to facilitate the storing of the digital information within the cross point memory array.
11. A re-writable memory, comprising:
a substrate;
a two-terminal cross point memory array formed above the substrate and including:
a first conductive array line oriented generally in an x-direction;
second conductive array lines, each of the second conductive array lines oriented generally in a y-direction substantially perpendicular to the x-direction;
two-terminal memory plugs, each memory plug having a first terminal in electrical communication with one of the first conductive array lines and a second terminal in electrical communication with one of the second conductive array lines, each memory plug configured to store information in a first data state and a second data state so as to collectively store elements of an information set;
a plurality of driver circuits, each driver circuit in electrical communication with the cross point array, the plurality of driver circuits operable to substantially simultaneously program multiple ones of the memory plugs to either the first data state or the second data state, wherein the plurality of driver circuits is further configured to program the first data state to a first portion of the memory plugs during a first cycle and the second data state to a second portion of the memory plugs during a second cycle that follows the first cycle, wherein the first portion and the second portion being mutually exclusive portions; and
logic circuits in electrical communication with a plurality of sensing circuits and with a burst clock, the logic circuits responsive to a burst clock signal from the burst clock so as to enter the information set to a page register in burst mode upon receiving the burst clock signal.
12. The re-writable memory of claim 11 and further comprising:
a data bus in electrical communication with the plurality of driver circuits, the data bus configured to transmit digital information to the plurality of driver circuits so as to facilitate the storing of the digital information within the cross point memory array.
13. A method of writing to a re-writable memory, comprising:
in a two-terminal cross point memory array having a block of two-terminal memory plugs each in electrical communication with one among a plurality of first conductive array lines and one among a plurality of second conductive array lines, transmitting a first electrical signal through said one first conductive array line during a first period of time and transmitting a second electrical signal through the selected one of said first conductive array lines during a second period of time;
during the first period of time, transmitting a third electrical signal through selected ones of said second conductive array lines, so as to write information to those memory plugs in electrical communication with both the selected one of said first conductive array lines and said selected second conductive array lines;
during the second period of time, transmitting a fourth electrical signal through selected others of said second conductive array lines, so as to write information to those memory plugs in electrical communication with both the selected one of said first conductive array lines and said selected others of said second conductive array lines; and
receiving an address signal, and decoding said address signal to determine an order in which to enter the information to be written to said memory plugs, so as to write information to said memory plugs in page mode.
14. The method of claim 13, wherein the first electrical signal and the second electrical signal have opposite polarities, so as to facilitate the writing of the information to the two-terminal memory plugs.
15. The method of claim 13, wherein the information further comprises binary 1’s and 0’s, the first electrical signal having a polarity representing a binary 1, and the second electrical signal having a polarity representing a binary 0.
16. A method of writing to a re-writable memory, comprising:
in a two-terminal cross point memory array having a block of two-terminal memory plugs each in electrical communication with one among a plurality of first conductive array lines and one among a plurality of second conductive array lines, transmitting a first electrical signal through said one first conductive array line during a first period of time and transmitting a second electrical signal through the selected one of said first conductive array lines during a second period of time;
during the first period of time, transmitting a third electrical signal through selected ones of said second conductive array lines, so as to write information to those memory plugs in electrical communication with both the selected one of said first conductive array lines and said selected second conductive array lines;
during the second period of time, transmitting a fourth electrical signal through selected others of said second conductive array lines, so as to write information to those memory plugs in electrical communication with both the selected one of said first conductive array lines and said selected others of said second conductive array lines; and
receiving a burst clock signal, wherein said transmitting a third electrical signal and transmitting a fourth electrical signal are carried out upon said receiving, so as to write information to said memory plugs in burst mode.
17. The method of claim 16, wherein the first electrical signal and the second electrical signal have opposite polarities, so as to facilitate the writing of the information to the two-terminal memory plugs.
18. The method of claim 16, wherein the information further comprises binary 1’s and 0’s, the first electrical signal having a polarity representing a binary 1, and the second electrical signal having a polarity representing a binary 0.
19. A re-writable memory, comprising:
a substrate;
a two-terminal cross point memory array formed above the substrate and including:
a first conductive array line;
second conductive array lines;
memory plugs having conductive oxide electrodes, each memory plug having a first terminal in electrical communication with the first conductive array line and a second terminal in electrical communication with one of the second conductive array lines, and each memory plug configured to assume a first electrical resistance that corresponds to a first data state in response to a first voltage and a second electrical resistance that corresponds to a second data state in response to a second voltage;
driver circuits, each driver circuit in electrical communication with the memory array and operable to deliver the first voltage during a first cycle to a first group of memory plugs so as to set the first group of memory plugs to the first data state in either page mode or burst mode and operable to deliver the second voltage during a second cycle following the first cycle, the second voltage delivered to a second group of memory plugs so as to set the second group of memory plugs to the second data state in either page mode or burst mode, the second group of memory plugs not including any memory plugs from the first group of memory plugs; and
address circuits in electrical communication with the driver circuits and configured to receive binary information and an address signal, the address circuits further configured to distribute the binary information to the decoder circuits according to the address signal, so as to facilitate writing of the received binary information to the two-terminal memory plugs in page mode.
20. The re-writable memory of claim 19 and further comprising:
a data bus having a plurality of data lines, each data line in electrical communication with an associated one of the driver circuits, and each configured to pass information to the associated driver circuit for storage in the cross point memory array so as to collectively facilitate the writing of a set of binary information to the cross point memory array.
21. A re-writable memory, comprising:
a substrate;
a two-terminal cross point memory array formed above the substrate and including:
a first conductive array line;
second conductive array lines;
memory plugs having conductive oxide electrodes, each memory plug having a first terminal in electrical communication with the first conductive array line and a second terminal in electrical communication with one of the second conductive array lines, and each memory plug configured to assume a first electrical resistance that corresponds to a first data state in response to a first voltage and a second electrical resistance that corresponds to a second data state in response to a second voltage;
driver circuits, each driver circuit in electrical communication with the memory array and operable to deliver the first voltage during a first cycle to a first group of memory plugs so as to set the first group of memory plugs to the first data state in either page mode or burst mode and operable to deliver the second voltage during a second cycle following the first cycle, the second voltage delivered to a second group of memory plugs so as to set the second group of memory plugs to the second data state in either page mode or burst mode, the second group of memory plugs not including any memory plugs from the first group of memory plugs; and
a burst clock in electrical communication with the driver circuits and configured to trigger the driver circuits to write binary information to the memory plugs in burst mode.
22. The re-writable memory of claim 21 and further comprising:
a data bus having a plurality of data lines, each data line in electrical communication with an associated one of the driver circuits, and each configured to pass information to the associated driver circuit for storage in the cross point memory array so as to collectively facilitate the writing of a set of binary information to the cross point memory array.
23. A re-writable memory, comprising:
a substrate; and
a two-terminal cross point memory array formed above the substrate and including:
a plurality of first conductive array lines;
a plurality of second conductive array lines, each of the plurality of second conductive array lines oriented substantially perpendicular to the plurality of first conductive array lines;
memory plugs, each memory plug having a first terminal in electrical communication with a first conductive array lines from the plurality of first conductive array lines and a second terminal in electrical communication with a second conductive array line from the plurality of second conductive array lines, the memory plugs configured to be able to be programmed into at least a high resistive state and a low resistive states, each resistive state being useful to represent stored information;
driver circuits, each driver circuit in electrical communication with the cross point array and operable to program the memory plugs into the at least two resistive states;
wherein the driver circuits are useful to program a first group of memory plugs in communication with the first conductive array line and a first group of second conductive array lines during a first cycle and are useful to program a second group of memory plugs in communication with the first conductive array line and a second group of second conductive array lines during a second cycle following the first cycle, the second group of memory plugs and the second group of second conductive array lines not including any memory plugs from the first group of memory plugs or the first group of second conductive array lines , wherein the programming of the first group of memory plugs cause them to have their resistive states raised and the programming of the second group of memory plugs cause them to have their resistive states lowered; and
address circuits in electrical communication with the driver circuits and configured to receive binary information and an address signal, the address circuits further configured to distribute the binary information to decoder circuits according to the address signal, so as to facilitate programming of the received binary information to the two-terminal memory plugs in page mode.
24. The re-writable memory of claim 23, wherein the second cycle sequentially follows the first cycle.
25. A re-writable memory, comprising:
a substrate; and
a two-terminal cross point memory array formed above the substrate and including:
a plurality of first conductive array lines;
a plurality of second conductive array lines, each of the plurality of second conductive array lines oriented substantially perpendicular to the plurality of first conductive array lines;
memory plugs, each memory plug having a first terminal in electrical communication with a first conductive array lines from the plurality of first conductive array lines and a second terminal in electrical communication with a second conductive array line from the plurality of second conductive array lines, the memory plugs configured to be able to be programmed into at least a high resistive state and a low resistive states, each resistive state being useful to represent stored information;
driver circuits, each driver circuit in electrical communication with the cross point array and operable to program the memory plugs into the at least two resistive states;
wherein the driver circuits are useful to program a first group of memory plugs in communication with the first conductive array line and a first group of second conductive array lines during a first cycle and are useful to program a second group of memory plugs in communication with the first conductive array line and a second group of second conductive array lines during a second cycle following the first cycle, the second group of memory plugs and the second group of second conductive array lines not including any memory plugs from the first group of memory plugs or the first group of second conductive array lines, wherein the programming of the first group of memory plugs cause them to have their resistive states raised and the programming of the second group of memory plugs cause them to have their resistive states lowered; and
a burst clock in electrical communication with the driver circuits and configured to trigger the driver circuits to write binary information to the two-terminal memory plugs in burst mode.
26. The re-writable memory of claim 25, wherein the second cycle sequentially follows the first cycle.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A method for invoking a Universal Service Interface (USI), comprising:
when determined that no valid short-lived user identity (ID) of a target user exists in an application for invoking the USI,
initiating, by the application, a service request to a USI system using a long-lived user ID of the target user,
receiving, by the application from the USI system, a short-lived user ID corresponding to the long-lived user ID used in the service request, and
initiating, by the application, a service request to the USI system using the short-lived user ID.
2. The method according to claim 1, further comprising:
if the application needs to initiate a service request to the USI system, searching, by the application, for existence of a valid short-lived user ID of the target user in the application.
3. The method according to claim 2, wherein the searching, by the application, for existence of a valid short-lived user ID of the target user in the application, comprises:
using, by the application, the long-lived user ID of the user as an index to search for a short-lived user ID corresponding to the long-lived user ID according to a binding relation between the long-lived user ID and the short-lived user ID; or
using, by the application, an application identity information of the user as an index to search for a short-lived user ID corresponding to the application identity information according to a binding relation between the application identity information of the user and the short-lived user ID.
4. The method according to claim 1, wherein before the receiving the short-lived user ID, the method further comprises:
searching, by the USI system, for existence of a short-lived user ID corresponding to the long-lived user ID;
sending, by the USI system, the short-lived user ID and a lifetime of the short-lived user ID corresponding to the long-lived user ID to the application.
5. The method according to claim 4, wherein before the sending the short-lived user ID, the method further comprises:
if no valid short-lived user ID corresponding to the long-lived user ID exists in the USI system, generating, by the USI system, the short-lived user ID and the lifetime of the short-lived user ID corresponding to the long-lived user ID.
6. The method according to claim 1, wherein after the receiving the short-lived user ID corresponding to the long-lived user ID used in the service request, the method further comprises:
storing, by the application, the short-lived user ID and a binding relation between the short-lived user ID and the long-lived user ID or a binding relation between the short-lived user ID and application identity information of the user.
7. The method according to claim 1, further comprising:
receiving, by the application, a message sent by the USI system requesting for the long-lived user ID;
sending, by the application, the long-lived user ID to the USI system; and
receiving, by the application from the USI system, a maintained short-lived user ID corresponding to the long-lived user ID.
8. The method according to claim 1, wherein the receiving a short-lived user ID corresponding to the long-lived user ID used in the service request comprises:
receiving, by the application from the USI system, the short-lived user ID and a lifetime of the short-lived user ID corresponding to the long-lived user ID used in the service request.
9. The method according to claim 8, wherein the short-lived user ID and the lifetime are generated and maintained by the USI system.
10. The method according to claim 8, wherein the short-lived user ID and the lifetime of the short-lived user ID are generated and maintained by an Authentication, Authorization and Accounting (AAA) server, and the method further comprises:
if the short-lived user ID and the lifetime of the short-lived user ID are generated or maintained by the AAA server, receiving, by the USI system, the short-lived user ID and the lifetime of the short-lived user ID from the AAA server.
11. A device for generating a short-lived user identity (ID) disposed for a Universal Service Interface (USI) system, comprising:
a first unit, configured to generate a short-lived user ID for a user, and maintain the short-lived user ID;
a second unit, configured to store a binding relation between the short-lived user ID and a long-lived user ID;
a third unit, configured to search in the second unit for a short-lived user ID corresponding to a long-lived user ID after receiving a service request carrying the long-lived user ID; and
a fifth unit, configured to send to an application a message requesting for a long-lived user ID corresponding to a short-lived user ID that is not maintained after receiving a service request carrying the short-lived user ID that is not maintained.
12. The device according to claim 11, further comprising:
a fourth unit, configured to send the short-lived user ID.
13. The device according to claim 11, wherein the device is disposed on an Authentication, Authorization and Accounting (AAA) server.
14. An application device, comprising:
a storage unit, configured to store a short-lived user ID, a long-lived user ID, application identity information of a user, and binding relations between the short-lived user ID, the long-lived user ID. the application identity information of the user;
a search unit, configured to search in the storage unit for a short-lived user ID of a target user;
a first sending unit, configured to send a service request to a Universal Service Interface (USI) system using the short-lived user ID of the target user if the search unit finds the short-lived user ID; and
a second sending unit, configured to send a service request to the USI system using a long-lived user ID if the search unit fails to find the short-lived user ID of the user.