1. A data converter for converting an input signal to
a plurality of digital bits, the data converter comprising:
n first comparison units for respectively comparing the input signal with n reference signals, each of the comparison units including a positive output end for outputting a first positive output and a negative output end for outputting a first negative output;
n second comparison units for respectively comparing the input signal with the n reference signals, each for outputting a second comparison units including a positive output end for outputting a second positive output and a negative output end for outputting a second negative output; and
an output unit electrically connected to the n first comparison units and the n second comparison units for generating digital bits corresponding to the n first comparison units and the n second comparison units, the output unit comprising:
n-1 interpolating units electrically connected to the n first comparison units and the n second comparison units, a kth interpolating unit being electrically connected to a kth and a kth+1 first comparison units and a kth and a kth+1 second comparison units for adding a third positive output to the first and second positive outputs of the n first comparison units and the n second comparison units and adding a third negative output to the first and second negative outputs of the n first comparison units and the n second comparison units; wherein when the kth and the kth+1 first comparison units perform an auto-zeroing process, the kth interpolating unit is capable of utilizing the second positive outputs of the kth and the kth+1 second comparison units for generating the third positive output and utilizing the second negative outputs of the kth and the kth+1 second comparison units for generating the third negative output;
wherein the output unit generates a digital bit interpolated between a digital bit corresponding to the kth second comparison unit and a digital bit corresponding to the kth+1 second comparison unit according to the third positive output and the third negative output in a differential manner.
2. The data converter of claim 1 wherein the output unit further comprises a plurality of latches electrically connected to the first comparison units, the second comparison units, and the interpolating units for outputting the digital bits.
3. The data converter of claim 1 wherein each of the first and second comparison units comprises an amplifier for amplifying a voltage difference between the input signal and a reference signal so as to generate a corresponding positive output and a corresponding negative output.
4. The data converter of claim 3 wherein each of the first and second comparison units further comprises a feedback circuit electrically connected between an output end and an input end of the amplifier, and when the comparison unit performs the auto-zeroing process, the feedback circuit conducts.
5. The data converter of claim 1 wherein the data converter further comprises a voltage dividing circuit for generating the n reference signals.
6. The data converter of claim 1 wherein the third positive output is interpolated between the second positive output of the kth and the kth+1 second comparison units, and the third negative output is interpolated between the second negative output of the kth and the kth+1 second comparison units.
7. A method for a data converter for converting an input signal to a plurality of digital bits, the data converter comprising:
n first comparison units for respectively comparing the input signal with n reference signals, each of the comparison units including a positive output end for outputting a first positive output and a negative output end for outputting a first negative output, a digital bit corresponding to a first comparison unit being generated from the first positive output and the first negative output in a differential manner;
n second comparison units for respectively comparing the input signal with the n reference signals, each of the second comparison units including a positive output end for outputting a second positive output and a negative output end for outputting a second negative output, a digital bit corresponding to a second comparison unit being generated from the second positive output and the second negative output in a differential manner, the method comprising:
when a kth and a kth+1 first comparison units perform an auto-zeroing process, utilizing the second positive outputs of a kth and a kth+1 second comparison units for generating a thin positive output, utilizing the second negative outputs of the kth and the kth+1 second comparison units for generating a third negative output, and generating a digital bit interpolated between a digital bit corresponding to the kth second comparison unit and a digital bit corresponding to the kth+1 second comparison unit according to the third positive output and the third negative output in a differential manner.
8. The method of claim 7 wherein the third positive output is interpolated between the second outputs of the kth and the kth+1 second comparison units, and the third negative output is interpolated between the second negative outputs of the kth and the kth+1 second comparison units.
9. A data converter for converting an input signal to a plurality of digital bits, the data converter comprising:
n first comparison units tin respectively comparing the input signal with n reference signals, each of the comparison units including a positive output end for outputting a first positive output and a negative output end for outputting a first negative output;
n second comparison units for respectively comparing the input signal with the n reference signals, each of the second comparison units including a positive output end for outputting a second positive output and a negative output end for outputting a second negative output; and
an output unit electrically connected to the n first comparison units and the n second comparison units for generating digital bits corresponding to the n first comparison units and the n second comparison units, the output unit comprising:
n-1 interpolating units electrically connected to the n first comparison units and the n second comparison units, a kth interpolating unit being electrically connected to a plurality of (kth to kth+p) first comparison units and a plurality of (kth to kth+p) second comparison units for adding a plurality of positive outputs to the first and second positive outputs of the n first comparison units and the n second comparison units and adding a plurality of negative outputs to the first and second negative outputs of the n first comparison units and the n first comparison units; wherein p is an integer, and when some first comparison units perform an auto-zeroing process, the kth interpolating unit is capable of utilizing the second positive outputs of the second comparison units for generating a plurality of positive outputs and utilizing the second negative outputs of some second comparison units for generating some negative outputs;
wherein the output unit generates a digital bit interpolated between a digital bit corresponding to the kth second comparison unit and a digital bit corresponding to the kth+p second comparison unit according to the positive outputs and the negative outputs in a differential manner.
10. The data converter of claim 9 wherein the output unit further comprises a plurality of latches electrically connected to the first comparison units, the second comparison units, and the interpolating units for outputting the digital bits.
11. The data converter of claim 9 wherein each of the first and second comparison units comprises an amplifier for amplifying a voltage difference between the input signal and a reference signal so as to generate a corresponding positive output and a corresponding negative output.
12. The data converter of claim 11 wherein each of the first and second comparison units further comprises a feedback circuit electrically connected between an output end and an input end of the amplifier, and when the comparison unit performs the auto-zeroing process, the feedback circuit conducts.
13. The data converter of claim 9 wherein each of the positive outputs is interpolated between the second positive outputs of the kth and the kth+p second comparison units, and each of the negative output is interpolated between the second negative outputs of the kth and the kth+p second comparison units.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A carry look-ahead circuit that generates a generate output for generating a carry, from a plurality of inverted generate inputs and a plurality of inverted propagate inputs to peer bits of a first operand and a second operand including a plurality of bits, the carry look-ahead circuit comprising:
a first circuit that receives the inverted generate inputs excluding the inverted generate input of a most significant bit among the inverted generate inputs and the inverted propagate inputs and generates an inverted pseudo generate signal of the generate output; and
a second 2-input circuit that receives the inverted generate input of the most significant bit among the inverted generate inputs and the inverted pseudo generate signal and outputs the generate output, and
wherein the second 2-input circuit is a 2-input NAND gate, and
a number of gate stages of a combination of the first circuit and the 2-input NAND gate is 4 when the first operand and the second operand respectively have 4 bits.
2. The carry look-ahead circuit according to claim 1, further comprising a circuit that receives the inverted propagate inputs and outputs a propagate output for generating the carry.
3. The carry look-ahead circuit according to claim 1, further comprising:
circuits that generate the respective inverted generate inputs as NANDs of the first operand and the second operand; and
circuits that generate the respective inverted propagate inputs as NORs of the first operand and the second operand.
4. The carry look-ahead circuit according to claim 2, further comprising:
a circuit that receives the propagate output and a carry input to output a propagating carry; and
a circuit that receives the generate output and the propagating carry and outputs a carry output.
5. A carry look-ahead method of generating a generate output for generating a carry, from a plurality of inverted generate inputs and a plurality of inverted propagate inputs to peer bits of a first operand and a second operand including a plurality of bits, the carry look-ahead method comprising:
receiving, using a first circuit, the inverted generate inputs excluding the inverted generate input of a most significant bit among the inverted generate inputs and the inverted propagate inputs to generate an inverted pseudo generate signal of the generate output; and
receiving, using a second 2-input circuit, the inverted generate input of the most significant bit among the inverted generate inputs and the inverted pseudo generate signal to output the generate output, and
wherein the second 2-input circuit is a 2-input NAND gate, and
a number of gate stages of a combination of the first circuit and the 2-input NAND gate is 4 when the first operand and the second operand respectively have 4 bits.
6. The carry look-ahead method according to claim 5, further comprising receiving the inverted propagate inputs to output a propagate output for generating the carry.
7. The carry look-ahead method according to claim 5, further comprising:
generating, using circuits, the inverted generate inputs as NANDs of the first operand and the second operand; and
generating, using circuits, the inverted propagate inputs as NORs of the first operand and the second operand.
8. The carry look-ahead method according to claim 6, further comprising:
receiving, using circuits the propagate output and a carry input to output a propagating carry; and
receiving, using circuits the generate output and the propagating carry to output a carry output.
9. A method of generating a generate output GG and a propagate output GP for generating a carry, from first to nth inverted generate inputs XG0 to XG(n\u22121) and first to nth inverted propagate inputs XP0 to XP(n\u22121) to a first operand and a second operand having n-bit width, n being a positive integer, the carry look-ahead method comprising:
generating an inverted pseudo generate signal XGG\u2032 obtained by dividing an inverted generate output XGG, which is a negative result of the generate output GG, by XG(n\u22121), GG, XGG, and XGG\u2032 being represented as follows:
GG=
G(n\u22121)+
P(n\u22121)\xb7G(n\u22122)+
P(n\u22121)\xb7P(n\u22122)\xb7G(n\u22123)+
P(n\u22121)\xb7P(n\u22122)\xb7P(n\u22123)\xb7G(n\u22124)+
. . .
P(n\u22121)\xb7P(n\u22122)\xb7P(n\u22123)\xb7 . . . \xb7G2\xb7G1+
P(n\u22121)\xb7P(n\u22122)\xb7P(n\u22123)\xb7 . . . \xb7P2\xb7P1\xb7G0,
XGG=
XP(n\u22121)+
XG(n\u22121)\xb7XP(n\u22122)+
XG(n\u22121)\xb7XG(n\u22122)\xb7XP(n\u22123)+
XG(n\u22121)\xb7XG(n\u22122)\xb7XG(n\u22123)\xb7XP(n\u22124)+
. . .
XG(n\u22121)\xb7XG(n\u22122)\xb7XG(n\u22123)\xb7 . . . \xb7XG2\xb7XP1+
XG(n\u22121)\xb7XG(n\u22122)\xb7XG(n\u22123)\xb7 . . . \xb7XG2\xb7XG1\xb7XG0, and
XGG\u2032=
XP(n\u22121)+
XP(n\u22122)+
XG(n\u22122)\xb7XP(n\u22123)+
XG(n\u22122)\xb7XG(n\u22123)\xb7XP(n\u22124)+
. . .
XG(n\u22122)\xb7XG(n\u22123)\xb7 . . . \xb7XG2\xb7XP1+
XG(n\u22122)\xb7XG(n\u22123)\xb7 . . . \xb7XG2\xb7XG1\xb7XG0; and
receiving, using a 2-input circuit, the nth inverted generate input XG(n\u22121) and the inverted pseudo generate signal XGG\u2032 to output the generate output GG.
10. The method according to claim 9, further comprising receiving the first to nth inverted propagate inputs XP0 to XP(n\u22121) to output the propagate output GP=!(XP(n\u22121)+XP(n\u22122)+ . . . +XP0).
11. The method according to claim 9, further comprising:
receiving first to nth bit inputs of the first operand and first to nth bit inputs of the second operand to output first to nth inverted generate signals XG0 to XG(n\u22121), respectively; and
receiving the first to nth bit inputs of the first operand and the first to nth bit inputs of the second operand to output first to nth inverted propagate signals XP0 to XP(n\u22121), respectively.