1. A heat pipe comprising:
an elongated casing having an evaporating section and a condensing section;
a wick disposed on an inner wall of the evaporating section of the casing;
at least one artery mesh disposed in the casing, the at least one artery mesh having a large portion and a small portion with an outer diameter smaller than that of the large portion, the small portion located within the evaporating section of the casing and being in direct physical contact with an inner surface of the wick, the large portion being in direct physical contact with an inner wall of the condensing section of the casing; and
working medium filled in the casing and saturating the wick and the at least one artery mesh;
wherein a bottom of the wick extends to the condensing section of the heat pipe, an axis of the large portion of the at least one artery mesh being offset from that of the small portion, a top of the large portion being in direct physical contact with the inner wall of the condensing section, and a bottom of the large portion being in direct physical contact with the wick.
2. The heat pipe of claim 1, wherein the heat pipe is a flat-type heat pipe, a substantially linear section of the large portion of the at least one artery mesh is in direct physical contact with the inner wall of the condensing section, and a substantially linear section of the small portion of the at least one artery mesh is in direct physical contact with the wick.
3. The heat pipe of claim 2, wherein the at least one artery mesh comprises a plurality of artery meshes disposed in the casing of the heat pipe and contacting each other.
4. The heat pipe of claim 2, wherein the at least one artery mesh comprises a plurality of artery meshes disposed in the casing of the heat pipe and spaced from each other.
5. The heat pipe of claim 2, wherein a thickness of the heat pipe is not larger than 2 mm, and a thickness of the wick is not larger than 0.1 mm.
6. The heat pipe of claim 1, wherein the at least one artery mesh is a hollow tube with an inner diameter ranging from 0.5 mm to 2 mm, the at least one artery mesh being made of a plurality of woven metal wires selected from a group consisting of copper wires and stainless steel wires.
7. A heat pipe comprising:
a flat tube-like metal casing having an evaporating section and a condensing section, a width of the casing being larger than a height of the casing;
a wick disposed on an inner wall of the evaporating section of the casing;
a plurality of artery meshes disposed in the casing, each artery mesh having a large portion being in direct physical contact with an inner wall of the condensing section of the casing and a small portion located within and being in direct physical contact with the wick; and
working medium filled in the casing and saturating the wick and the artery meshes;
wherein a bottom of the wick extends to the condensing section of the heat pipe, an axis of the large portion of each of the artery meshes being offset from that of the small portion, a top of the large portion being in direct physical contact with the inner wall of the condensing section, and a bottom of the large portion being in direct physical contact with the wick.
8. The heat pipe of claim 7, wherein a thickness of the heat pipe is not larger than 2 mm, and a thickness of the wick is not larger than 0.1 mm.
9. The heat pipe of claim 7, wherein the artery mesh is a hollow tube with an inner diameter ranging from 0.5 mm to 2 mm just for the condensed working medium flowing therethrough.
10. The heat pipe of claim 7, wherein the artery meshes are one of woven copper wires and woven stainless steel wires.
11. A heat pipe comprising:
a metal casing including an evaporating section and a condensing section;
a wick structure arranged at the evaporating section, the wick structure disposed around an inner wall of the evaporating section;
at least a hollow, interwoven artery mesh including a first mesh portion arranged at the evaporating section and a second mesh portion arranged at the condensing section, the first mesh portion located within and being in direct physical contact with the wick structure, the first mesh portion having a diameter smaller than that of the second mesh portion, the second mesh portion being in direct physical contact with an inner wall of the condensing section;
another wick structure arranged at a bottom portion of the condensing section and connected with the wick structure in the evaporating section, a bottom portion of the at least an artery mesh being disposed on and in direct physical contact with said another wick structure; and
working medium received in the casing.
12. The heat pipe of claim 11, wherein the at least an artery mesh is a plurality of artery meshes, and the artery meshes are evenly spaced from each other in the metal casing.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A packaged stacked semiconductor device which comprises bumps serving as external electrode terminals, the bumps being provided on both a front surface and a back surface of the device, and which is stacked on another semiconductor device, substrate, or board having electrode terminals so that the bumps are directly and electrically connected to the electrode terminals, comprising:
a semiconductor substrate having through-electrodes which penetrate through the substrate;
on the front surface side of the semiconductor substrate, an LSI formation surface on which a plurality of circuit elements are formed, a multi-layer wiring section provided on the LSI formation surface and connected to the circuit elements, a first insulating film provided on the top surface of the multi-layer wiring section, an additional wiring layer provided on the first insulating film for connecting a final wiring layer of the multi-layer wiring section to the through-electrodes andor post electrodes, a second insulating film formed so as to cover the front surface of the semiconductor substrate, exclusive of tip end surfaces of the post electrodes, and external connection bumps connected to the tip end surfaces of the post electrodes, wherein the second insulating film has a thickness greater than that of the semiconductor substrate, and rigidity of the semiconductor device is substantially secured by the second insulating film; and
on the back surface side of the semiconductor substrate, a third insulating film formed so that tip end surfaces of the through-electrodes are exposed, bump formation regions which are provided on the third insulating film and are connected to the tip end surfaces of the through-electrodes by means of wiring, a fourth insulating film formed on the third insulating film, and external connection bumps connected to the bump formation regions through apertures provided in the fourth insulating film.
2. A packaged stacked semiconductor device according to claim 1, wherein the wiring on the third insulating film is formed through screen printing or ink jetting by use of metal nanoparticles.
3. A packaged stacked semiconductor device according to claim 2, wherein the wiring is covered with a nitride film, and the nitride film is formed from any of silicon carbonitride, silicon oxynitride, silicon oxycarbonitride, and silicon nitride, which are chemical species generated through catalytic decomposition caused by bringing, into contact with a heated catalyst, one or more silazane compounds selected from among hexamethyldisilazane, tetramethyldisilazane, octamethyltrisilazane, hexamethylcyclotrisilazane, tetraethyltetramethylcyclotetrasilazane, and tetraphenyldimethyldisilazane.
4. A packaged stacked semiconductor device according to claim 1, in which the stacked semiconductor device carries, on its top surface, an additional semiconductor device, and is mounted on and connected to the top surface of a daughterboard formed of a multi-layer wiring board, wherein the stacked semiconductor device is aligned with the additional semiconductor device so that connection regions of these devices are overlapped with one another, and the external connection bumps are connected to the additional semiconductor device.
5. A packaged stacked semiconductor device according to claim 4, which includes a spacer via which a peripheral portion of the additional semiconductor device is supported by the daughterboard.
6. A packaged stacked semiconductor device according to claim 4, which is connected to one or more additional semiconductor devices in three dimensions with a substrate or a heat radiation plate being inserted between the stacked semiconductor device and the additional semiconductor device(s).
7. A packaged stacked semiconductor device according to claim 1, wherein the second insulating film has a thickness of 40 to 200 mm, the semiconductor substrate has a thickness of 10 to 50 mm, and the fourth insulating film has a thickness of 30 mm or less.
8. A packaged stacked semiconductor device according to claim 1, wherein, on the back surface of the semiconductor substrate, the bump formation regions connected, by the wiring, to the tip end surfaces of the through-electrodes are relocated by means of an additional wiring layer to arbitrary positions with respect to the positions of the through-electrodes.
9. A packaged stacked semiconductor device according to claim 1, in which simultaneously with formation of holes for the through-electrodes in a plurality of the semiconductor substrates, which are portions of a semiconductor wafer arranged in a grid pattern, scribe lines of a predetermined with for cutting the semiconductor wafer into individual semiconductor devices are formed on the semiconductor wafer; and the second insulating film is formed so as to cover the front surface of the substrate and the scribe lines, so that each of the semiconductor devices obtained through cutting along the scribe lines has end surfaces covered with the insulating film.
10. A packaged stacked semiconductor device according to claim 1, wherein the first and second insulating films are formed on the semiconductor substrate in the form of semiconductor wafer, and the wiring on the back surface of the semiconductor substrate is formed through ink jetting by use of copper nanoparticles.
11. A packaged stacked semiconductor device according to claim 1, wherein a nitride film is employed as an insulating film which covers the side walls of the holes for the through-electrodes, and the nitride film is formed on the side walls by bringing, into contact with the side walls, any of silicon carbonitride, silicon oxynitride, silicon oxycarbonitride, and silicon nitride, which are chemical species generated through catalytic decomposition caused by bringing, into contact with a heated catalyst, one or more silazane compounds selected from among hexamethyldisilazane, tetramethyldisilazane, octamethyltrisilazane, hexamethylcyclotrisilazane, tetraethyltetramethylcyclotetrasilazane, and tetraphenyldimethyldisilazane.
12. A packaged stacked semiconductor device according to claim 11, wherein the through-electrodes are formed by charging metal nanoparticles in the holes covered with the insulating film.
13. A packaged stacked semiconductor device according to claim 12, wherein the through-electrodes are treated with atomic hydrogen generated through catalytic decomposition caused by bringing a gas of a hydrogen-containing compound into contact with a heated catalyst, for reduction of a surface-oxidized film andor removal of an organic substance.
14. A method for producing a packaged stacked semiconductor device which comprises bumps serving as external electrode terminals, the bumps being provided on both a front surface and a back surface of the device, and which is stacked on another semiconductor device, substrate, or board having electrode terminals so that the bumps are directly and electrically connected to the electrode terminals, comprising:
providing a plurality of semiconductor substrates, which are portions of a semiconductor wafer arranged in a grid pattern formed by scribe lines;
forming a plurality of circuit elements on the front surface of each semiconductor substrate, the front surface serving as an LSI formation surface;
forming a multi-layer wiring section on the LSI formation surface so that the section is connected to the circuit elements;
providing through-electrodes in the semiconductor substrate;
forming a first insulating film on the multi-layer wiring section;
forming an additional wiring layer for connecting a final wiring layer of the multi-layer wiring section to the through-electrodes andor post electrodes;
forming a second insulating film on the front surface of the semiconductor substrate, after formation of the post electrodes, and exposing tip end portions of the post electrodes;
grinding the back surface of the semiconductor substrate so that tip end portions of the through-electrodes are exposed;
forming a third insulating film on the back surface of the semiconductor substrate so that tip end surfaces of the through-electrodes are exposed;
providing bump formation regions on the third insulating film formed on the back surface of the semiconductor substrate so that the bump formation regions are connected to the thus-exposed tip end surfaces of the through-electrodes by means of wiring;
forming a fourth insulating film on the wiring;
forming bumps on the bump formation regions through apertures provided in the fourth insulating film, wherein the second insulating film is formed to have a thickness greater than that of the semiconductor substrate, and the fourth insulating film is formed to have a thickness smaller than that of the substrate, so that rigidity of the semiconductor device is substantially secured by the second insulating film; and
forming bumps on the tip end portions of the post electrodes on the front side of the semiconductor substrate.
15. A packaged stacked semiconductor device production method according to claim 14, wherein the wiring on the third insulating film on the back surface of the semiconductor substrate is formed through screen printing or ink jetting by use of metal nanoparticles.
16. A packaged stacked semiconductor device production method according to claim 15, wherein the wiring is covered with a nitride film, and the nitride film is formed from any of silicon carbonitride, silicon oxynitride, silicon oxycarbonitride, and silicon nitride, which are chemical species generated through catalytic decomposition caused by bringing, into contact with a heated catalyst, one or more silazane compounds selected from among hexamethyldisilazane, tetramethyldisilazane, octamethyltrisilazane, hexamethylcyclotrisilazane, tetraethyltetramethylcyclotetrasilazane, and tetraphenyldimethyldisilazane.
17. A packaged stacked semiconductor device production method according to claim 14, wherein formation of the bumps on the front and back sides of the semiconductor substrate is carried out before or after the semiconductor wafer is cut and separated into individual semiconductor devices.
18. A packaged stacked semiconductor device production method according to claim 14, wherein formation of the through-electrodes, which penetrate through the semiconductor substrate, is carried out through a process in which holes for the through-electrodes are provided in the substrate; an insulating film is formed on the side walls of the holes at such a low temperature that does not adversely affect the multi-layer wiring section; material for the through-electrodes is charged into the holes; and the through-electrodes are connected to a predetermined wiring layer in the multi-layer wiring section.
19. A packaged stacked semiconductor device production method according to claim 14, wherein formation of the through-electrodes, which penetrate through the semiconductor substrate, is carried out through a process in which holes for the through-electrodes are provided in the substrate; an insulating film is formed on the side walls of the holes at such a low temperature that does not adversely affect the multi-layer wiring section; an aperture is formed in the multi-layer wiring section to thereby provide a portion for connecting the through-electrodes to a predetermined wiring layer in the multi-layer wiring section; and material for the through-electrodes is charged into the holes and the aperture serving as the connection portion.
20. A packaged stacked semiconductor device production method according to claim 14, wherein holes for the through-electrodes are provided in the semiconductor substrate in the form of semiconductor wafer on which numerous semiconductor elements of the same type have been simultaneously formed, while scribe lines having a predetermined width for cutting the semiconductor substrate into individual semiconductor devices are formed on the substrate; and the second insulating film is formed so as to cover the front surface of the semiconductor substrate and the scribe lines, so that a semiconductor device obtained through cutting along the scribe lines has end surfaces covered with the insulating film.
21. A packaged stacked semiconductor device production method according to claim 14, wherein the first and second insulating films are formed on the semiconductor substrate in the form of semiconductor wafer, and the wiring on the back surface of the semiconductor substrate is formed through ink jetting by use of copper nanoparticles.
22. A packaged stacked semiconductor device production method according to claim 14, wherein a nitride film is employed as an insulating film which covers the side walls of the holes for the through-electrodes, and the nitride film is formed on the side walls by bringing, into contact with the side walls, any of silicon carbonitride, silicon oxynitride, silicon oxycarbonitride, and silicon nitride, which are chemical species generated through catalytic decomposition caused by bringing, into contact with a heated catalyst, one or more silazane compounds selected from among hexamethyldisilazane, tetramethyldisilazane, octamethyltrisilazane, hexamethylcyclotrisilazane, tetraethyltetramethylcyclotetrasilazane, and tetraphenyldimethyldisilazane.
23. A packaged stacked semiconductor device production method according to claim 22, wherein the through-electrodes are formed by charging metal nanoparticles in the holes covered with the insulating film.
24. A packaged stacked semiconductor device production method according to claim 23, wherein the through-electrodes are treated with atomic hydrogen generated through catalytic decomposition caused by bringing a gas of a hydrogen-containing compound into contact with a heated catalyst, to thereby reduce a surface-oxidized film andor to remove an organic substance.