1. A processor implemented method to perform a set of performance tests on an application in a continuous deployment pipeline, the method comprising:
identifying, with a decision engine executed by a processor, a set of code changes between a baseline build and a new build, the baseline build and the new build being two distinct builds in a performance test environment;
obtaining, with a test engine executed by the processor, a baseline test result by executing a set of customized test scripts on the baseline build in the performance test environment, the baseline build including a first code base that successfully completed the set of performance tests in the continuous deployment pipeline;
testing, with the test engine executed by the processor, the new build by executing the set of customized test scripts on the new build in the performance test environment to obtain a new test result, the new build including a second code base being tested in the continuous deployment pipeline; and
determining, with a decision engine executed by the processor, a performance value by comparing the baseline test result and the new test result.
2. The method of claim 1, wherein the performance value comprises at least one of:
analyzing a system performance value for each of the baseline build and the new build, the system performance value corresponding to performance of a client device;
analyzing a server code change performance value for each of the baseline build and the new build, the server code change performance value corresponding to performance of at least one of the first code base and the second code base on a server device; and
analyzing a client device code change performance value for each of the baseline build and the new build, the client device code change performance value corresponding to performance of at least one of the first code base and the second code base on a client device.
3. The method of claim 1, further comprising simultaneously executing the set of customized test scripts on the baseline build and the new build.
4. The method of claim 1, further comprising monitoring the set of code changes to determine and periodically build a new code base based on the set of code changes received.
5. The method of claim 1, wherein determining the performance value comprises analyzing the baseline test result and the new test result for at least one of a performance trend and a performance problem.
6. The method of claim 1, wherein determining the performance value comprises correlating the performance value to a specific code change between the first code base and the second code base.
7. The method of claim 1, further comprising providing the performance value as a performance report.
8. The method of claim 1, further comprising obtaining the baseline build from a build repository.
9. The method of claim 1, further comprising storing the performance value in a test result repository.
10. The method of claim 1, further comprising generating a load on at least one of a client device and a server.
11. A system to perform a set of performance tests on an application in a continuous deployment pipeline, the system comprising:
a processor configured to execute:
a test engine to:
obtain a baseline test result by executing a set of customized test scripts on a baseline build in a performance test environment, the baseline build including a first code base that successfully completed the set of performance tests in the continuous deployment pipeline; and
execute the set of customized test scripts on a new build in the performance test environment to obtain a new test result, the new build including a second code base being tested in the continuous deployment pipeline; and
a decision engine to:
identify a set of code changes between the baseline build and the new build, the baseline build and the new build being two distinct builds in the performance test environment; and
determine a performance value based on comparison of the baseline test result and the new test result.
12. The system of claim 11, further comprising a data store to store at least one of the following:
the baseline build, the new build, the baseline test result, the new test result, and the performance values.
13. The system of claim 11, further comprising a monitor engine to monitor the set of code changes and build a new code base based on the set of code changes received.
14. The system of claim 11, further comprising an analysis engine to perform at least one of the following:
analyze the baseline test result and the new test result for at least one of a performance trend and a performance problem;
correlate the performance value to a specific portion of the second code base; and
generate a performance report to identify the performance values.
15. An apparatus useable with a continuous deployment pipeline, the apparatus comprising:
a test device to perform a set of performance tests in the continuous deployment pipeline;
a memory to store a set of instructions; and
a processor coupled to the memory to execute the set of instructions to:
identify a set of code changes between a baseline build and a new build, the baseline build and the new build being two distinct builds in a performance rest environment;
obtain a baseline test result by executing a set of customized test scripts on the baseline build in the performance test environment, the baseline build including a first code base that the set of performance tests were successfully executed on in the continuous deployment pipeline;
execute the set of customized test scripts on the new build in the performance test environment to obtain a new test result, the new build including a second code base being tested in the continuous deployment pipeline; and
determine a performance value based on a comparison of the baseline test result and the new test result.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A method of forming at least one wire on a substrate, the substrate comprising at least one conductive region, an insulating layer disposed on the substrate, and the insulating layer comprising at least one recess exposing the conductive region, the method comprising:
forming a barrier layer on a surface of the insulating layer and the recess;
forming a continuous and uniform conductive layer on a surface of the barrier layer, the conductive layer comprising an aluminum layer;
forming a seed layer on a surface of the conductive layer and interlaying the conductive layer between the seed layer and the barrier layer; and
forming a metal layer on a surface of the seed layer, and the metal layer filling up the recess.
2. The method of claim 1 wherein the substrate comprises a semiconductor wafer or a silicon-on-insulator substrate (SOI substrate).
3. The method of claim 1 wherein the conductive region comprises a source of a transistor, a gate of a transistor, a drain of a transistor, a lower level wire, a landing pad, or a resistor.
4. The method of claim 1 wherein the recess is a via hole of a dual damascene structure.
5. The method of claim 1 wherein the barrier layer comprises a silicon nitride layer, a titanium nitride layer (TiN layer), a tantalum nitride layer (TaN layer), or a tantalum nitridetantalum (TaNTa) composite metal layer.
6. The method of claim 1 wherein a thickness of the conductive layer ranges from 5 to 400 angstroms (\u212b).
7. The method of claim 1 wherein the method for forming the conductive layer comprises a chemical vapor deposition (CVD) process or an atomic layer deposition ALD) process.
8. The method of claim 1 wherein the seed layer is a copper layer formed by a physical vapor deposition (PVD) process.
9. The method of claim 1 wherein the seed layer is a copper alloy layer formed by a physical vapor deposition (PVD) process.
10. The method of claim 1 wherein a thickness of the seed layer ranges from 5 to 2000 angstroms (\u212b).
11. The method of claim 1 wherein the metal layer is formed by an electric copper plating (ECP) process.
12. A method of forming at least one dual damascene wire on a substrate, the substrate comprising at least one conductive region, an insulating layer disposed on the substrate, and the insulating layer comprising at least one trench pattern and via hole pattern stacked from top to bottom exposing the conductive region, the method comprising:
forming a barrier layer on a surface of the insulating layer, the trench pattern, and the via hole pattern;
forming a continuous and uniform conductive layer on a surface of the barrier layer, the conductive layer comprising an aluminum layer;
forming a seed layer on a surface of the conductive layer and interlaying the conductive layer between the seed layer and the barrier layer; and
forming a metal layer on a surface of the seed layer, and the metal layer filling up the trench pattern and the via hole pattern.
13. The method of claim 12 wherein the substrate comprises a semiconductor wafer or a silicon-on-insulator substrate (SOI substrate).
14. The method of claim 12 wherein the conductive region comprises a source of a transistor, a gate of a transistor, a drain of a transistor, a lower level wire, a landing pad, or a resistor.
15. The method of claim 12 wherein the barrier layer comprises a silicon nitride layer, a titanium nitride layer (TiN layer), a tantalum nitride layer (TaN layer), or a tantalum nitridetantalum (TaNTa) composite metal layer.
16. The method of claim 12 wherein the method for forming the conductive layer comprises a chemical vapor deposition (CVD) process or an atomic layer deposition (ALD) process, and a thickness of the conductive layer ranges from 5 to 400 angstroms (\u212b).
17. The method of claim 12 wherein the seed layer is a copper layer formed by a physical vapor deposition (PVD) process, and a thickness of the seed layer ranges from 5 to 2000 angstroms (\u212b).
18. The method of claim 12 wherein the seed layer is a copper alloy layer formed by a physical vapor deposition (PVD) process, and a thickness of the seed layer ranges from 5 to 2000 angstroms (\u212b).
19. The method of claim 12 wherein the metal layer is formed by an electric copper plating (ECP) process.