1. A circuit arrangement for the interference-free evaluation of signals, in particular of output signals of at least one knocking sensor, having at least two inputs to which one sensor can be connected potential-free or two sensors can be connected with ground reference, having a differential amplifier which is connected to the inputs, and having an output stage, which optionally converts the differential signal furnished by the amplifier into a signal with ground reference, characterized in that the circuit arrangement can be operated in two operating modes, and the first operating mode is employed with potential-free connection and a symmetrical signal, and the second operating mode is employed with a potential-referred connection and an asymmetrical signal.
2. The circuit arrangement of claim 1, characterized in that the operating mode can be switched over from outside between symmetrical and asymmetrical.
3. The circuit arrangement of claim 2, characterized in that the choice of the operating mode can be programmed from outside via a control pin.
4. The circuit arrangement of one of the foregoing claims, characterized in that a passive coupling network is present between the sensor or sensors and the actual signal processing circuit.
5. The circuit arrangement of claim 4, characterized in that the passive coupling network is symmetrical and includes a first capacitor (CL) between the terminals of the sensor and two further capacitors (C1a, C2a), which are connected on the one hand to the sensor and on the other, via resistors (R1a, R2a), to the inputs (E1, E2) of the signal processing circuit (S) and, via resistors (R1b, R2b), to a terminal to which a reference voltage (Ur) is applied.
6. The circuit arrangement of one of the foregoing claims, characterized in that signal processing stages, and in particular at least one bandpass filter andor at least one rectifier andor at least one integrator, are connected downstream of the differential amplifier (V).
7. The circuit arrangement of claim 6, characterized in that the components in the group comprising the amplifier, bandpass filter, rectifier, and integrator are constructed employing the switched-capacitor technique.
8. The circuit arrangement of one of the foregoing claims, characterized in that the output stage (A) of the signal processing circuit (S) is connected to a microcomputer via an analogdigital converter, and the signal evaluation is done in this microcomputer.
9. The circuit arrangement of one of the foregoing claims, characterized in that it is employed for evaluating the output signals of two knocking sensors, which are connected via unshielded lines in potential-free fashion each to two inputs of the signal processing circuit, or for the evaluation of the output signals of four knocking sensors, which are connected by shielded lines each to one input of the signal processing circuit.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A graphics system comprising:
a frame buffer;
a multipurpose memory;
a memory controller configured to allocate a texture buffer for storing texture data in the multipurpose memory, to allocate an image buffer for storing image data in the multipurpose memory, to allocate an accumulation buffer for storing accumulation buffer data in the multipurpose memory, wherein the multipurpose memory is configured to have data stored in the image buffer, the texture buffer, and the accumulation buffer at the same time, and wherein at least two of the image buffer, the texture buffer and the accumulation buffer are accessed with different interleaving patterns; and
a processing device coupled to the frame buffer and the multipurpose memory, wherein the processing device is configured to read texture data, image data, and accumulation buffer data from the texture buffer, image buffer, and accumulation buffer respectively, and to perform texturing operations, image processing operations, and accumulation operations using the texture data, image data, and accumulation buffer data respectively.
2. The graphics system of claim 1, wherein a device driver executing on a host computer is configured to direct the allocation of the image buffer, the texture buffer mid the accumulation buffer with respective sizes as requested by one or more software processes executing on the host computer.
3. The graphics system of claim 1, wherein a device driver executing on a host computer is configured to direct a relocation of buffers including the image buffer, the texture buffer and the accumulation buffer within the address space of the multipurpose memory to reduce memory fragmentation.
4. The graphics system of claim 1, wherein at least two of the image buffer, the texture buffer and the accumulation buffer are configured with different data resolutions.
5. The graphics system of claim 1, wherein at least two of the image buffer, the texture buffer and the accumulation buffer are accessed with different address scrambling techniques.
6. The graphics system of claim 1, wherein the processing device is configured to receive graphics primitives, to apply the texel data from the texture buffer to the graphics primitives, and to store results of said texture application into the frame buffer.
7. The graphics system of claim 6, wherein the processing device is configured to store results of said image processing operations in the image buffer or in the frame buffer.
8. The graphics system of claim 6, wherein the processing device is configured to store results of said accumulation operations in the accumulation buffer or in the frame buffer.
9. The graphics system of claim 1 further comprising a video output processor, wherein the processing device is configured to store pixels in the frame buffer, wherein the video output processor is configured to read said pixels from the frame buffer and generate a video output from said pixels.
10. A graphics system comprising:
a frame buffer;
a multipurpose memory;
a memory controller configured to allocate a texture buffer for storing texture data in the multipurpose memory, to allocate an image buffer for storing image data in the multipurpose memory, to allocate an accumulation buffer for storing accumulation buffer data in the multipurpose memory, wherein the multipurpose memory is configured to have data stored in the image buffer, the texture buffer, and the accumulation buffer at the same time, and wherein at least two of the image buffer, the texture buffer and the accumulation buffer are accessed with different address scrambling techniques; and
a processing device coupled to the frame buffer and the multipurpose memory, wherein the processing device is configured to read texture data, image data, and accumulation buffer data from the texture buffer, image buffer, and accumulation buffer respectively, and to perform texturing operations, image processing operations, and accumulation operations using the texture data, image data, and accumulation buffer data respectively.
11. The graphics system of claim 10, wherein a device driver executing on a host computer is configured to direct the allocation of the image buffer, the texture buffer and the accumulation buffer with respective sizes as requested by one or more software processes executing on the host computer.
12. The graphics system of claim 10, wherein a device driver executing on a host computer is configured to direct a relocation of buffers including the image buffer, the texture buffer and the accumulation buffer within the address space of the multipurpose memory to reduce memory fragmentation.
13. The graphics system of claim 10, wherein at least two of the image buffer, the texture buffer and the accumulation buffer are configured with different data resolutions.
14. The graphics system of claim 10, wherein the processing device is configured to receive graphics primitives, to apply the texel data from the texture buffer to the graphics primitives, and to store results of said texture application into the frame buffer.
15. The graphics system of claim 14, wherein the processing device is configured to store results of said image processing operations in the image buffer or in the frame buffer.
16. The graphics system of claim 14, wherein the processing device is configured to store results of said accumulation operations in the accumulation buffer or in the frame buffer.
17. The graphics system of claim 10, further comprising a video output processor, wherein the processing device is configured to store pixels in the frame buffer, wherein the video output processor is configured to read said pixels from the frame buffet and generate a video output from said pixels.