1. A backpack for convenient charging, said backpack comprising:
a backpack body with a battery storage space to accommodate a storage battery unit;
at least one strap connected to the backpack body, where at least one strap has a fixture for fixing a product to be charged and a power cable output port proximal to the fixture;
wherein the backpack body further includes at least one cable passage leading from the battery storage space to the power cable output port to accommodate at least one power cable each with a first end and a second end, wherein at least one of the first end and the second end of the at least one power cable is connected to the storage battery unit to be charged.
2. The backpack as in claim 1, wherein one of said at least one cable passages is inside the backpack body and said fixture comprises a bag mounted on the front side of the at least one strap.
3. The backpack as in claim 1, wherein said power cable output port is installed above fixture.
4. The backpack as in claim 1, wherein said at least one cable passage is inside the backpack body and between the power cable output port and the battery storage space.
5. The backpack as in claim 1, wherein the unit further comprises a storage battery unit installed in storage battery space and at least one power cable is introduced through a first of the at least one cable passages.
6. The backpack as in claim 1, wherein the backpack body is furnished with at least one solar panel and the backpack body includes a cable passage leading from storage battery space towards the installing place of solar panel to accommodate a power cable; wherein a first end and a second end of the power cable are connected to the storage battery unit and solar panel.
7. The backpack as in claim 1, wherein the backpack body is furnished with at least one additional storage space to accommodate other articles and another cable passage leading from the at least one additional storage space to accommodate other power cables.
8. The backpack of claim 1, wherein the power cable is further comprising an output terminal.
9. The backpack of claim 1, wherein the power cable further includes a Bluetooth actuator to actuate and energize the Bluetooth unit on the product to be charged.
10. The backpack of claim 1, wherein said backpack body further includes GPS unit.
11. The backpack of claim 1, wherein the power cable output port is comprised of a plus (+) shaped center portion.
12. A backpack for convenient charging, said backpack comprising:
a backpack body with a battery storage space to accommodate a storage battery unit;
two straps connected to the backpack body, where at least one strap has a fixture for fixing a product to be charged and a power cable output port proximal to the fixture and wherein the power cable output port is installed above fixture;
wherein the backpack body further includes at least one cable passage leading from the battery storage space to the power cable output port to accommodate at least one power cable each with a first end and a second end, wherein at least one of the first end and the second end of the at least one power cable is connected to the storage battery unit to be charged.
13. The backpack as in claim 12, wherein one of said at least one cable passages is inside the backpack body and said fixture comprises a bag mounted on the front side of the at least one strap.
14. The backpack as in claim 12, wherein said at least one cable passage is inside the backpack body and between the power cable output port and the battery storage space.
15. The backpack as in claim 12, wherein the unit further comprises a storage battery unit installed in storage battery space and at least one power cable is introduced through a first of the at least one cable passages.
16. The backpack as in claim 12, wherein the backpack body is furnished with at least one solar panel and the backpack body includes a cable passage leading from storage battery space towards the installing place of solar panel to accommodate a power cable; wherein a first end and a second end of the power cable are connected to the storage battery unit and solar panel.
17. The backpack as in claim 2, wherein the backpack body is furnished with at least one additional storage space to accommodate other articles and another cable passage leading from the at least one additional storage space to accommodate other power cables.
18. The backpack for convenient charging of claim 12, wherein the power cable is further comprising an output terminal.
19. The backpack for convenient charging of claim 12, wherein the power cable further includes a Bluetooth actuator to actuate and energize the Bluetooth unit on the product to be charged.
20. The backpack for of claim 12, wherein said backpack body further includes GPS unit.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A frequency adjustment circuit that adjusts an oscillation frequency based on a time constant set by a time constant circuit, comprising:
a zapping circuit that generates frequency adjustment data in response to a reset signal inputted periodically to the zapping circuit, the zapping circuit comprising a zapping device and the frequency adjustment data corresponding to a status of the zapping device;
a frequency adjustment data latch circuit that retains the frequency adjustment data generated by the zapping circuit in response to a latch clock inputted periodically to the frequency adjustment data latch circuit, the latch clock being generated after a corresponding reset signal is generated; and
a time constant adjustment circuit that receives the frequency adjustment data retained in the frequency data latch circuit and adjusts the time constant of the time constant circuit based on the frequency adjustment data.
2. The frequency adjustment circuit of claim 1, further comprising a reset signal generation circuit that generates the reset signal in accordance with a start of an enable signal and a latch clock generation circuit that generates the latch clock in accordance with an end of the enable signal.
3. The frequency adjustment circuit of claim 2, further comprising an interface circuit that receives data that is serially transferred from a computer, receives a transfer clock of the serially-transferred data and receives a chip enable signal so as to output the chip enable signal as the enable signal.
4. The frequency adjustment circuit of claim 2, further comprising an interface circuit that receives data that is serially transferred from a computer, receives address data that specifies an address of a device, receives a chip enable signal, receives transfer clocks of the serially-transferred data, the address data and the chip enable signal, and verifies that the received address data corresponds to a predetermined address so as to generate an address verify signal which is used as the enable signal.
5. The frequency adjustment circuit of claim 4, further comprising an address verify signal register that retains the address verify signal in response to the chip enable signal.
6. The frequency adjustment circuit of claim 5, wherein the address verify signal register takes in the address verify signal in accordance with a start of the chip enable signal and is reset in accordance with an end of the chip enable signal.
7. The frequency adjustment circuit of claim 1, wherein the zapping device comprises a fuse.
8. The frequency adjustment circuit of claim 1, wherein the time constant circuit comprises a resistor and a capacitor.
9. A frequency adjustment circuit that adjusts an oscillation frequency based on a time constant set by a time constant circuit, comprising:
an interface circuit that receives a chip enable signal and data serially transferred from a computer, and receives transfer clocks of the chip enable signal and the serially-transferred data;
a serial data counter that counts a number of bits of the serially-transferred data by counting the transfer clocks;
a reset signal generation circuit that generates a reset signal in accordance with a start of the chip enable signal;
a latch clock generation circuit that generates a latch clock in accordance with an end of the chip enable signal and a count output of the serial data counter;
a zapping circuit that generates frequency adjustment data in response to the reset signal, the zapping circuit comprising a zapping device and the frequency adjustment data corresponding to a status of the zapping device;
a frequency adjustment data latch circuit that retains the frequency adjustment data generated by the zapping circuit in response to the latch clock; and
a time constant adjustment circuit that receives the frequency adjustment data retained in the frequency data latch circuit and adjusts the time constant of the time constant circuit based on the frequency adjustment data.
10. The frequency adjustment circuit of claim 9, wherein the zapping device comprises a fuse.
11. The frequency adjustment circuit of claim 9, wherein the time constant circuit comprises a resistor and a capacitor.
12. A frequency adjustment circuit that adjusts an oscillation frequency based on a time constant set by a time constant circuit, comprising:
an interface circuit that receives data serially transferred from a computer, receives address data that specifies an address data of a device, receives a chip enable signal, receives transfer clocks of the serially-transferred data, the address data and the chip enable signal, and verifies that the address data corresponds to a predetermined address so as to generate an address verify signal;
a serial data counter that counts a number of bits of the serially-transferred data by counting the transfer clocks;
a reset signal generation circuit that generates a reset signal in accordance with a start of the address verify signal;
a latch clock generation circuit that generates a latch clock in accordance with an end of the address verify signal and a count output of the serial data counter;
a zapping circuit that generates frequency adjustment data in response to the reset signal, the zapping circuit comprising a zapping device and the frequency adjustment data corresponding to a status of the zapping device;
a frequency adjustment data latch circuit that retains the frequency adjustment data generated by the zapping circuit in response to the latch clock; and
a time constant adjustment circuit that receives the frequency adjustment data retained in the frequency data latch circuit and adjusts the time constant of the time constant circuit based on the frequency adjustment data.
13. The frequency adjustment circuit of claim 12, further comprising an address verify signal register that retains the address verify signal in response to the chip enable signal.
14. The frequency adjustment circuit of claim 12, wherein the address verify signal register takes in the address verify signal in accordance with a start of the chip enable signal and is reset in accordance with an end of the chip enable signal.
15. The frequency adjustment circuit of claim 12 wherein the zapping device comprises a fuse.
16. The frequency adjustment circuit of claim 12, wherein the time constant circuit comprises a resistor and a capacitor.