1. An encoding method of generating a low-density parity check convolutional code of a coding rate of \u2153 and a time varying period of 3 from a low-density parity check convolutional code of a coding rate of \xbd and a time varying period of 3, the low-density parity check convolutional code of the coding rate of \xbd and the time varying period of 3 being defined based on:
a first parity check polynomial in which (a1%3, a2%3, a3%3) and (b1%3, b2%3, b3%3) are any of (0, 1, 2), (0, 2, 1), (1, 0, 2), (1, 2, 0), (2, 0, 1) and (2, 1, 0) of a parity check polynomial represented by equation 1-1;
a second parity check polynomial in which (A1%3, A2%3, A3%3) and (B1%3, B2%3, B3%3) are any of (0, 1, 2), (0, 2, 1), (1, 0, 2), (1, 2, 0) and (2, 0, 1), (2, 1, 0) of a parity check polynomial represented by equation 1-2; and
a third parity check polynomial in which (\u03b11%3, \u03b12%3, \u03b13%3) and (\u03b21%3, \u03b22%3, \u03b23%3) are any of (0, 1, 2), (0, 2, 1), (1, 0, 2), (1, 2, 0), (2, 0, 1) and (2, 1, 0) of a parity check polynomial represented by equation 1-3, wherein c % d (where c and d are any integers) represents a remainder after dividing c by d, the method comprising the steps of:
inserting, using an encode circuit, known information into 3k pieces of information Xj (where j’s are any indexes of 6i, 6i+1, 6i+2, . . . , 6(i+k\u22121)+3, 6(i+k\u22121)+4, 6(i+k\u22121)+5, and j’s are different from each other) of 6 k bits of information X6i, X6i+1, X6i+2, X6i+3, X6i+4, X6i+5, . . . , X6(i+k\u22121), X6(i+k\u22121)+1, X6(i+k\u22121)+2, X6(i+k\u22121)+3, X6(i+k\u22121)+4, X6(i+k\u22121)+5 such that, of remainders after dividing values of the 3k different indexes j’s by 3, the number of remainders which become 0 is k, the number of remainders which become 1 is k and the number of remainders which become 2 is k, the 6k bits of information made by extracting information from information part of one period of encoded outputs including the information part and parity part, and by arranging the extracted information in output order of the encoded outputs, the one period of the encoded outputs composed of 12k (k is a natural number) bits of the information part and the parity part which are the encoded outputs using the low-density parity check convolutional code of a coding rate of \xbd; and
obtaining, using the encode circuit, the parity part from the information including the known information,
wherein:
the equation 1-1 is
(Da1+Da2+Da3)X(D)+(Db1+Db2+Db3)P(D)=0,
the equation 1-2 is
(DA1+DA2+DA3)X(D)+(DB1+DB2+DB3)P(D)=0; and
the equation 1-3 is
(D\u03b11+D\u03b12+D\u03b13)X(D)+(D\u03b21+D\u03b22+D\u03b23)P(D)=0,
where:
X(D) is a polynomial representation of information X and P(D) is a parity polynomial representation;
a1, a2 and a3 are integers (where a1\u2260a2\u2260a3) and b1, b2 and b3 are integers (where b1\u2260b2\u2260b3);
A1, A2 and A3 are integers (where A1\u2260A2\u2260A3) and B1, B2 and B3 are integers (where B1\u2260B2\u2260B3); and
\u03b11, \u03b12 and \u03b13 are integers (where \u03b11\u2260\u03b12\u2260\u03b13) and \u03b21, \u03b22 and \u03b23 are integers (where \u03b21\u2260\u03b22\u2260\u03b23).
2. An encoder that creates a low-density parity check convolutional code from a convolutional code, comprising a computing section that computes a parity part using the encoding method according to claim 1.
3. A decoder that decodes a low-density parity check convolutional code using belief propagation, the decoder comprising:
a row processing computing section that performs row processing computation using a check matrix corresponding to the parity check polynomials used for the encoder according to claim 2;
a column processing computing section that performs column processing computation using the check matrix; and
a determining section that estimates a codeword using computation results in the row processing computing section and the column processing computing section.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
What is claimed is:
1. A charge-pumping circuit for low-supply voltage comprising:
a plurality of first transistors, wherein the source of each said first transistor is coupled to the drain of successive said first transistor so that all of said first transistors are connected in series; wherein the drain of the first of said first transistors is coupled to a supply voltage, the source of the last of said first transistors is coupled to the output of said pumping circuit, and the gate and drain of the last of said first transistors are coupled;
a plurality of second transistors, wherein each second transistor is coupled to a corresponding said first transistor, the drain and gate of each said second transistor is coupled and connected with the gate of the corresponding said first transistor, and the source and the well of each said second transistor is coupled and connected to the drain of said corresponding first transistor;
a plurality of said third transistors, wherein each said third is coupled to one of said first transistors, the well and the source of each said third transistor is coupled and connected to the well of the corresponding said first transistor, the drain of each said third transistor is coupled to the source of the corresponding said first transistor, the gate of said third transistors corresponding to the first of said first transistors is coupled to a clock;
each gate of the transistors of said third transistor group, except for the first transistor of said third transistor group, is coupled to the drain of the corresponding transistor of said first transistor group;
a plurality of capacitors, each said capacitor has a corresponding transistor of said first transistor group exclusively, except the first transistor of said first transistor group, one ends of said capacitors are coupled to the drains of the corresponding transistors of said first transistor group, while the other ends of said capacitors are interlacedly coupled to said clock and the inverted signal of said clock; and
a secondary charge-pumping circuit, which supplies bias-voltage to the gate of each transistor of said first transistor group.
2. The charge-pumping circuit as claimed in claim 1, wherein the secondary charge-pumping circuit comprising:
a plurality of fourth transistors, the source of each said fourth transistor is coupled to the drain of its successive said so that all said fourth transistors are connected in a series, the drain of the first transistor of said fourth transistors is coupled and connected to said power supply, the source of the last of said fourth transistors is coupled to the output of said pumping circuit, the gate and drain of said fourth transistors are coupled, said first transistors, excluding the last of said first transistors, have corresponding said fourth transistors, excluding the first and the second of said fourth transistors, respectively, and the gate of each said first transistor is coupled to the gate of said corresponding fourth transistors; the rule of the correspondence between said fourth transistors and said first transistors is that said clocks and said inverted signals of said second capacitors coupled to the drains of said fourth transistors are equal to said clocks and said inverted signals of said capacitors coupled to the drains of said first transistors;
a plurality of fifth transistors, wherein each said fifth has a corresponding said fourth transistors exclusively, the well and source of each said fifth transistor are coupled to the well of said corresponding fourth transistors, the drain of each said fifth transistor is coupled to the source of the corresponding fourth transistors; and the gate of the first of said fifth transistors corresponding to the first of said fourth transistors, is coupled to said clock; the gates of other said fifth transistors are coupled to the drain of said corresponding fourth transistors; and
a plurality of second capacitors, wherein each said capacitor has a corresponding said fourth transistor except the first of said fourth transistors, one end of each said second capacitor is coupled to the drain of said corresponding fourth transistor, the other end of each said second capacitor is interlacedly coupled to said clock or said inverted signal.
3. charge-pumping circuit as claimed in claim 1, wherein said transistors are NMOS transistors so that the output terminal of said charge-pumping circuit outputs a positive bias voltage.
4. The charge-pumping circuit as claimed in claim 1, wherein said transistors are PMOS transistors so that the output terminal of said charge-pumping circuit outputs negative bias voltage.
5. The charge-pumping circuit as claimed in claim 4, wherein said supply voltage is zero volts.
6. A charge-pumping circuit for low-supply voltage, comprising:
a first charge-pumping unit, comprising;
a first transistor, wherein the drain of said first transistor is coupled to a supply voltage; and
a second transistor, wherein the well and source of said second transistor is coupled to the well of said first transistor, the drain of said second transistor is coupled to the source of said first transistor, and the gate of said second transistor receives a signal from clock;
a second charge-pumping unit, comprising:
a third transistor, wherein the drain and gate of said third transistor are coupled, the source of said third transistor is the output terminal of said second charge-pumping circuit;
a fourth transistor, wherein the well and source of said fourth transistor are coupled to the well of said third transistor, the drain of said fourth transistor is coupled to the source of said third transistor, and the gate of said fourth transistor is coupled to the drain of said third transistor; and
a first capacitor, wherein, one end of said first capacitor is coupled to the drain of said third transistor, while the other end of said first capacitor is coupled to said clock;
at least one third charge-pumping unit, comprising:
a fifth transistor, wherein the drain of said fifth transistor is coupled to the source of said first transistor, the source of said fifth transistor is coupled to the drain of said third transistor;
a sixth transistor, wherein the well and source of said sixth transistor are coupled to the well of said fifth transistor, the drain of said sixth transistor is coupled to the source of said fifth transistor, and the gate of said sixth transistor is coupled to the drain of said fifth transistor;
a second capacitor, one end of said capacitor is coupled to the drain of said fifth transistor, the other end of said second capacitor is coupled to said inverted clock;
a seventh transistor, wherein the drain and gate of said seventh transistor are coupled to the gate of said fifth transistor, the source and substrate of said seventh transistor are coupled to the drain of said fifth transistor; and
a secondary charge-pumping circuit, which supplies bias voltage to the gates of said first and said fifth transistors; and
wherein said clock and said inverted signal are interlacedly coupled to said second transistor, said second capacitor and said first capacitor, respectively.
7. The charge-pumping circuit as claimed in claim 6, wherein, there are a plurality third charge-pumping circuits in which several stages of said charge-pumping circuits are connected in series.
8. The charge-pumping circuit as claimed in claim 6, wherein said transistors are NMOS transistors so that the output terminal of said charge-pumping circuit outputs a positive bias voltage.
9. The charge-pumping circuit as claimed in claim 6, wherein said transistors are PMOS transistors so that the output terminal of said charge-pumping circuit outputs a negative bias voltage.
10. The charge-pumping circuit as claimed in claim 9, wherein said supply voltage is zero volts.
11. The charge-pumping circuit as claimed in claim 6, wherein the transistors of the first charge-pumping circuit are in the same well; the transistors of the second charge-pumping circuit are in another well; the fifth and sixth transistors of the third charge-pumping circuit are in one well, but the seventh transistor is in another well; all the transistors are placed in one deep-well for triple well technology.