1. A programmable logic device (PLD) comprising a serial data interface, the serial data interface including:
a first pin adapted to transmit a chip select signal from within the PLD directly to a first pin of a serial PROM;
a second pin adapted to transmit a configuration clock signal from within the PLD directly to a second pin of the serial PROM;
a third pin adapted to transmit a read command and an address signal from within the PLD directly to a third pin of the serial PROM, and
a fourth pin adapted to receive a configuration bitstream directly from a fourth pin of the serial PROM,
the PLD including one or more of the following configuration modes:
a first configuration mode wherein the read command transmitted from the third pin is hardwired within the PLD; and
a second configuration mode wherein the read command transmitted from the third pin is user programmable within the PLD.
2. The PLD of claim 1, wherein the serial data interface conforms to a Serial Peripheral Interface (SPI) standard.
3. The PLD of claim 2, wherein the serial PROM is a flash PROM that conforms to the SPI standard.
4. The PLD of claim 1, wherein the serial data interface further includes a fifth pin adapted to transmit an initialization signal from the PLD directly to a fifth pin of the serial PROM.
5. The PLD of claim 1, wherein the serial data interface is implemented with dedicated circuitry within the PLD.
6. The PLD of claim 1, wherein the serial data interface is implemented with programmable logic within the PLD.
7. The PLD of claim 1, wherein the serial data interface is adapted to transmit sequentially to the serial PROM the chip select signal, the read command, the address signal, and the configuration clock signal, and to receive in response from the serial PROM the configuration bitstream.
8. The PLD of claim 1, wherein the PLD is an FPGA.
9. An apparatus comprising:
a serial flash PROM comprising a serial data interface, the serial data interface including:
a first pin adapted to receive a chip select signal;
a second pin adapted to receive a configuration clock signal;
a third pin adapted to receive a read command and an address signal; and
a fourth pin adapted to transmit a configuration bitstream in response to the read command and address signal; and
a programmable logic device (PLD) comprising a serial data interface, the serial data interface including:
a first pin adapted to transmit the chip select signal from within the PLD directly to the first pin of the serial flash PROM;
a second pin adapted to transmit the configuration clock signal from within the PLD directly to the second pin of the serial flash PROM;
a third pin adapted to transmit the read command and the address signal from within the PLD directly to the third pin of the serial flash PROM, and
a fourth pin adapted to receive the configuration bitstream directly from the fourth pin of the serial flash PROM,
the PLD including a first configuration mode wherein the read command transmitted from the third pin is user programmable within the PLD.
10. The apparatus of claim 9, wherein the serial data interfaces of the PLD and serial flash PROM conform to a Serial Peripheral Interface (SPI) standard.
11. The apparatus of claim 9, wherein the serial data interface of the PLD and the serial data interface of the serial flash PROM each further includes a fifth pin, the fifth pin of the PLD adapted to transmit an initialization signal from the PLD directly to the fifth pin of the serial PROM.
12. The apparatus of claim 9, wherein the serial data interface of the PLD is implemented with dedicated circuitry within the PLD.
13. The apparatus of claim 9, wherein the serial data interface of the PLD is implemented with programmable logic within the PLD.
14. The apparatus of claim 9, wherein the serial data interface of the PLD is adapted to transmit sequentially to the serial data interface of the serial flash PROM the chip select signal, the read command, the address signal, and the configuration clock signal, and to receive in response from the serial data interface of the serial flash PROM the configuration bitstream.
15. The apparatus of claim 9, wherein the PLD is an FPGA.
16. The PLD of claim 1, wherein the hardwired read command is a multi-bit opcode.
17. The PLD of claim 1, wherein the PLD includes both the first and second configuration modes.
18. The PLD of claim 17, including one or more additional pins adapted to receive the user programmable read command.
19. The PLD of claim 1, wherein the first configuration mode is an SPI03 mode and the second configuration mode is an SPIX mode.
20. The PLD of claim 9 including one or more additional pins adapted to receive the user programmable read command.
21. The PLD of claim 9, wherein the user programmable read command is a multi-bit opcode.
22. The apparatus of claim 9, in which the PLD includes a second configuration mode wherein the read command transmitted from the third pin is hardwired within the PLD.
23. The apparatus of claim 22, wherein the first configuration mode is an SPIX mode and the second configuration mode is an SPI03 mode.
24. A programmable logic device (PLD) comprising a serial data interface, the serial data interface including:
a first pin adapted to transmit a chip select signal from within the PLD directly to a first pin of a serial PROM;
a second pin adapted to transmit a configuration clock signal from within the PLD directly to a second pin of the serial PROM;
a third pin adapted to transmit a read command and an address signal from within the PLD directly to a third pin of the serial PROM, and
a fourth pin adapted to receive a configuration bitstream directly from a fourth pin of the serial PROM,
the PLD including a first configuration mode wherein the read command transmitted from the third pin is hardwired within the PLD.
25. The PLD of claim 24, wherein the hardwired read command is a multi-bit opcode.
26. The PLD of claim 24, in which the PLD includes a second configuration mode wherein the read command transmitted from the third pin is user programmable within the PLD.
27. The PLD of claim 26 including one or more additional pins adapted to receive the user programmable read command.
28. The PLD of claim 26, wherein the first configuration mode is an SPI03 mode and the second configuration mode is an SPIX mode.
29. The PLD of claim 24, wherein the serial data interface is implemented with dedicated circuitry within the PLD.
30. The PLD of claim 24, wherein the serial data interface is implemented with programmable logic within the PLD.
31. The PLD of claim 24, wherein the PLD is an FPGA.
32. A programmble logic device (PLD) comprising a serial data interface, the serial data interface including:
a first pin adapted to transmit a chip select signal from within the PLD directly to a first pin of a serial PROM;
a second pin adapted to transmit a configuration clock signal from within the PLD directly to a second pin of the serial PROM;
a third pin adapted to transmit a read command and an address signal from within the PLD directly to a third pin of the serial PROM, and
a fourth pin adapted to receive a configuration bitstream directly from a fourth pin of the serial PROM,
the PLD including a first configuration mode wherein the read command transmitted from the third pin is user programmable within the PLD.
33. The PLD of claim 32 including one or more additional pins adapted to receive the user programmable read command.
34. The PLD of claim 32, wherein the user programmable read command is a multi-bit opcode.
35. The PLD of claim 32, wherein the serial data interface is implemented with dedicated circuitry within the PLD.
36. The PLD of claim 32, wherein the serial data interface is implemented with programmable logic within the PLD.
37. The PLD of claim 32, wherein the PLD is an FPGA.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A mask comprising a substrate, and a pattern having a transmission factor formed on the substrate by using a material, wherein an optical path length difference between light beams respectively passing the pattern and an area adjacent thereto is greater than (m) and less than (m) , where is a wavelength of incident light, and m is an integer.
2. A mask comprising a substrate, and a pattern having a reflection factor formed on the substrate by using a material, wherein an optical path length difference between light beams respectively passing the pattern and an area adjacent thereto is greater than (m) and less than (m) , where is a wavelength of incident light, and m is an integer.
3. A mask according to claim 1, wherein the wavelength is in the following range:
150 nm<<440 nm.
4. A mask according to claim 2, wherein the wavelength is in the following range:
150 nm<<440 nm.
5. An exposure method comprising a step of transferring, by using a mask according to claim 1, a pattern image of the mask onto a photosensitive substrate.
6. An exposure method comprising a step of transferring, by using a mask according to claim 2, a pattern image of the mask onto a photosensitive substrate.
7. An exposure method comprising a projection exposure step of projecting, by using a mask according to claim 1, a pattern image of the mask onto a photosensitive substrate, and a two-light-flux interference exposure step of forming a pattern image by using interference of two light fluxes.
8. An exposure method comprising a projection exposure step of projecting, by using a mask according to claim 2, a pattern image of the mask onto a photosensitive substrate, and a two-light-flux interference exposure step of forming a pattern image by using interference of two light fluxes.
9. An exposure apparatus having an exposure mode for exposing the photosensitive substrate with a pattern of the mask by using an exposure method according to one of claims 5 to 8.
10. A method for manufacture of a device, comprising a process of transferring a pattern of a reticle to a wafer by using an exposure method according to one of claims 5 to 8, and a process of developing the wafer.