1. A memory system having:
a non-volatile solid-state memory for storing user data, the non-volatile memory having a plurality of physical blocks, each physical block being organized into a plurality of physical pages, each physical block being erasable as a unit and each physical page being writable and readable as a unit,
a mapping data memory arranged to store:
(i) first mapping data indicating, for each of a plurality of logical blocks, a mapping between each logical block and a corresponding first one of said physical blocks;
(ii) for each logical block, a respective first page pointer for indicating a page of the corresponding first physical block, and
(iii) second mapping data indicating for each logical page of each logical block, the physical page of the corresponding first physical block to which data in respect of that logical page was last written; and
a memory controller arranged to perform a write operation in relation to any logical page of any of said logical blocks, said write operation in relation to any given logical page including the steps of:
(a) using the respective first page pointer to identify a physical page of the corresponding first physical block,
(b) writing data to the identified physical page,
(c) updating the second mapping data to indicate the identified physical page as the physical page to which data in respect of the given logical page was last written; and
(d) updating the respective first page pointer to indicate a new physical page of the corresponding first physical block.
2. A memory system according to claim 1 wherein the memory controller is arranged in said write operation to perform an additional step (e) of writing in said identified physical page data indicating the identity of the given logical page.
3. A memory system having:
a non-volatile solid-state memory for storing user data, the non-volatile memory having a plurality of physical blocks, each physical block being organized into a plurality of physical pages, each physical block being erasable as a unit and each physical page being writable and readable as a unit,
a mapping data memory arranged to store:
(i) first mapping data indicating, for each of a plurality of logical blocks, a mapping between each logical block and a corresponding first one of said physical blocks;
(ii) for each logical block, a respective first page pointer for indicating a page of the corresponding first physical block, and
a memory controller arranged to perform a write operation in relation to any logical page of any of said logical blocks, said write operation in relation to any given logical page including the steps of:
(a) using the respective first page pointer to identify a physical page of the corresponding first physical block,
(b) writing user data to the identified physical page,
(c) writing in said identified physical page identity data indicating the identity of the given logical page; and
(d) updating the pointer according to a predefined sequence;
whereby the user data and identity data written to said identified physical page supersede any user data and identity data in a physical page of the corresponding first physical block previously associated with the logical page.
4. A memory system according to claim 1, in which at least a portion of said mapping data memory is stored in a random access memory.
5. A memory system according to claim 1 in which at least a portion of said mapping data memory is stored in a non-volatile random access memory.
6. A memory system according to claim 1 in which at least a portion of said mapping data memory is within said non-volatile solid state memory.
7. A memory system according to claim 1 wherein the mapping data memory is arranged to store:
a table having a plurality of entries, wherein each entry is uniquely addressable by and associated with a logical block, and wherein each entry has a field for registering said page pointer.
8. A memory system according to claim 1 wherein the mapping data memory is arranged to store:
a table having a plurality of entries, wherein each entry is uniquely addressable by and associated with a logical block, and wherein each entry has a field for registering said corresponding first physical block.
9. A memory system according to claim 8 when dependent on claim 7 wherein said page pointer and said fields are portions of a single first table.
10. A memory system according to claim 8 when dependent on claim 5 wherein the first table is stored in the non-volatile random access memory.
11. A memory system according to claim 9 or claim 10 in which each said entry further includes a first tag for indicating whether the corresponding logical block is associated with a first physical block.
12. A memory system having:
a first non-volatile memory for storing user data, the first non-volatile memory having a plurality of physical blocks, each physical block being organized into a plurality of physical pages, each physical block being erasable as a unit and each physical page being writable and readable as a unit,
a second memory, the second memory being organized into a plurality of bytes, the bytes being randomly accessible, each byte being writable and readable as a unit, the second memory being arranged to store data mapping logical blocks to corresponding physical blocks;
a memory controller arranged to store user data in said first non-volatile memory;
at least a portion of the second memory being non-volatile, at least a portion of the mapping data being stored in said non-volatile memory.
13. A memory system according to claim 12, the second memory being arranged to store:
a table comprising a plurality of entries, wherein each entry is uniquely addressable by and associated with a physical block number, and each entry records a usage status of a respective associated physical block of first non-volatile memory.
14. A memory system according to claim 13, wherein the said status takes at least four states:
a first state indicating the physical block is erased and free for allocation,
a second state indicating the physical block is currently being mapped to a logical block and used for storing user data,
a third state indicating the physical block is ready for erasure, and
a fourth state indicating the physical block is not fit for read or write.
15. A memory system according to claim 14,
a memory controller arranged to write pages of said physical blocks of first non-volatile memory for storing user data, and at certain times erasing one or more of said physical blocks, upon which the erased blocks are free for allocation, the steps of updating an entry of said fourth table in second non-volatile memory of an associated physical block, including:
from first state to second state when said physical block is allocated for writing data,
from second state to third state when said physical block is de-allocated for writing data,
from third state to first state when said physical block has been erased from any state to fourth state when writing or erasing said physical block returns an error condition.
16. A memory system having:
a non-volatile solid-state memory for storing user data, the non-volatile memory having a plurality of physical blocks, each physical block being organized into a plurality of physical pages, each physical block being erasable as a unit and each physical page being writable and readable as a unit,
a mapping data memory storing data indicating, for each of a plurality of logical blocks, a mapping between the logical blocks and corresponding first ones of physical blocks;
a memory controller arranged to perform a write operation in relation to any logical page of any of said logical blocks, said write operation comprising storing data relating to a said logical page of a said logical block in a physical page of the corresponding first physical block,
said memory controller being arranged, upon a physical block fullness criterion being met in respect of the first physical block, to associate a second physical block with the corresponding logical block, and subsequently to write data relating to logical pages of that logical block in pages of the second physical block.
17. A memory system according to claim 16 in which at least a portion of said mapping data memory is a random access memory.
18. A memory system according to claim 17 in which at least a portion of said mapping data memory is a non-volatile random access memory.
19. A memory system according to any of claims 16 to 18 in which said physical block fullness criterion is that all pages of said first physical block have been written to.
20. A memory system having:
a non-volatile memory for storing user data, the non-volatile memory having a plurality of physical blocks, each physical block being organized into a plurality of physical pages, each physical block being erasable as a unit and each physical page being writable and readable as a unit,
a mapping data memory arranged to store:
(i) first mapping data indicating, for each of the plurality of logical blocks, a mapping between each logical block and a corresponding first one of said physical blocks;
(ii) third mapping data indicating, for at least one of the plurality of logical blocks, a mapping between the or each logical block and a corresponding second one of said physical blocks;
a memory controller arranged to perform a write operation into the non-volatile solid-state memory of user data in relation to any specified one of the plurality of logical blocks,
said write operation including, in the case of a logical block which is one of said at least one logical blocks, writing user data into a determined one of the corresponding first and second physical blocks.
21. A memory system according to claim 20 in which said write operation including, in the case of a logical block which is one of said at least one logical blocks, the steps of:
(a) determining if a fullness criterion in respect of first physical block is met;
(b) if determination in (a) is negative, identifying a physical page of the corresponding first physical block;
(c) if determination in (a) is positive, identifying a physical page of the corresponding second physical block; and
(d) writing user data to the identified physical page.
22. A memory system according to claim 21 in which the memory controller is operative, upon receiving a write command specifying a write operation in respect of a plurality of logical pages of a given logical block, to determine said fullness criterion would be met if user data in respect of some, but not all, the specified logical pages is written to the first physical block, and if said determination is positive writing data in respect of some of said specified logical pages to the first physical block and data in respect of other of said logical pages to the second physical block.
23. (canceled)
24. (canceled)
25. (canceled)
26. (canceled)
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A method of inspecting a semiconductor device, the method comprising:
applying an initial energy from an energy source to a first location of a conductive layer of the semiconductor device;
measuring a resultant energy passing through the conductive layer using a probe applied at a second location of the conductive layer;
analyzing the measured resultant energy passing through the conductive layer; and
determining a presence of an inconsistency in the conductive layer based on the analyzing.
2. The method of claim 1, wherein the analyzing comprises comparing a magnitude of the measured resultant energy with a magnitude of the initial energy, and wherein the presence of the inconsistency is determined when the magnitude of the measured resultant energy is less than about 50% of the magnitude of the initial energy.
3. The method of claim 1, wherein the analyzing comprises establishing an expected magnitude of the resultant energy based on a magnitude of the initial energy and comparing a magnitude of the measured resultant energy with the expected magnitude of the resultant energy, and wherein the presence of the inconsistency is determined when the magnitude of the measured resultant energy is less than the expected magnitude of the resultant energy.
4. The method of claim 1, further comprising identifying a severity of the inconsistency.
5. The method of claim 6, wherein the severity of the inconsistency is identifiable as a pit within the conductive layer when a magnitude of the measured resultant energy is about 60-70% of an expected magnitude of the resultant energy.
6. The method of claim 6, wherein the severity of the inconsistency is identifiable as a partial break within the conductive layer when a magnitude of the measured resultant energy is less than about 50% of an expected magnitude of the resultant energy.
7. The method of claim 6, wherein the severity of the inconsistency is identifiable as an oxide bridge within the conductive layer when a magnitude of the measured resultant energy is about 0-10% of an expected magnitude of the resultant energy.
8. The method of claim 6, wherein the severity of the inconsistency is identifiable as a complete break of the conductive layer when a magnitude of the measured resultant energy is about 0% of an expected magnitude of the resultant energy.
9. The method of claim 2, further comprising identifying a approximate location of the inconsistency in the conductive layer by:
applying the initial energy at a third location of the conductive layer, the third location being adjacent to the first location;
measuring a second resultant energy passing through the conductive layer between the third location and the probe; and
identifying the first location to be the location of the inconsistency in the conductive layer when a magnitude of the measured second resultant energy is greater than a magnitude of the measured resultant energy.
10. The method of claim 1, wherein the conductive layer being inspected is an elongated copper layer formed using a damascene or a dual damascene process.
11. A system for inspecting a semiconductor device, the system comprising:
an energy source operable to apply an initial energy to a first location of a conductive layer of the semiconductor device;
a probe operable to measure a resultant energy passing through the conductive layer at a second location of the conductive layer; and
a processor operable to:
analyze the measured resultant energy passing through the conductive layer; and
determine a presence of an inconsistency in the conductive layer based on the analyzing.
12. The system of claim 11, wherein a tip of the probe comprises a conductive contact surface operable to be applied at the second location, the conductive contact surface having a dimension of lesser than about 0.1 microns.
13. The system of claim 11, wherein the processor analyzes by comparing a magnitude of the measured resultant energy with a magnitude of the initial energy, and wherein the processor determines the presence of the inconsistency when the magnitude of the measured resultant energy is less than about 50% of the magnitude of the initial energy.
14. The system of claim 11, wherein the processor analyzes by establishing an expected magnitude of the resultant energy based on a magnitude of the initial energy and comparing a magnitude of the measured resultant energy with the expected magnitude of the resultant energy, and wherein the processor determines the presence of the inconsistency when the magnitude of the measured resultant energy is less than the expected magnitude of the resultant energy.
15. The system of claim 11, wherein the processor is further operable to identify a severity of the inconsistency.
16. The system of claim 15, wherein the processor is operable to identify the severity of the inconsistency as a pit within the conductive layer when a magnitude of the measured resultant energy is about 60-70% of an expected magnitude of the resultant energy.
17. The system of claim 15, wherein the processor is operable to identify the severity of the inconsistency as a partial break within the conductive layer when a magnitude of the measured resultant energy is less than about 50% of an expected magnitude of the resultant energy.
18. The system of claim 15, wherein the processor is operable to identify the severity of the inconsistency as an oxide bridge within the conductive layer when a magnitude of the measured resultant energy is about 0-10% of an expected magnitude of the resultant energy.
19. The system of claim 15, wherein the processor is operable to identify the severity of the inconsistency as a complete break of the conductive layer when a magnitude of the measured resultant energy is about 0% of an expected magnitude of the resultant energy.
20. The system of claim 11, wherein:
the energy source is further operable to apply the initial energy at a third location of the conductive layer, the third location being adjacent to the first location;
the probe is further operable to measure a second resultant energy passing through the conductive layer between the third location and the probe; and
the processor is further operable to identify the first location to be a approximate location of the inconsistency in the conductive layer when a magnitude of the measured second resultant energy is greater than a magnitude of the measured resultant energy.
21. The system of claim 11, wherein the conductive layer being inspected is an elongated copper layer formed using a damascene or a dual damascene process.