1. A method for manufacturing a microcrystalline semiconductor film, comprising the steps of:
forming a seed crystal over an insulating film by a plasma CVD method under a first condition;
forming a first microcrystalline semiconductor film on the seed crystal by a plasma CVD method under a second condition; and
forming a second microcrystalline semiconductor film on the first microcrystalline semiconductor film by a plasma CVD method under a third condition,
wherein the first condition is a condition that a deposition gas containing silicon is diluted by setting a flow rate of hydrogen to more than or equal to 50 times and less than or equal to 1000 times that of the deposition gas, and a pressure in a process chamber is higher than or equal to 67 Pa and lower than or equal to 50000 Pa,
wherein the second condition is a condition that a deposition gas containing silicon is diluted by setting a flow rate of hydrogen to more than or equal to 100 times and less than or equal to 2000 times that of the deposition gas, and a. pressure in the process chamber is higher than or equal to 1333 Pa and lower than or equal to 50000 Pa, and
wherein the third condition is a condition that a pressure in the process chamber is higher than or equal to 1333 Pa and lower than or equal to 50000 Pa, and a first period in which Microcrystalline semiconductor is deposited and a second period which is longer than the first period and in which an amorphous semiconductor region formed in the first period is selectively etched are alternately performed.
2. The method for manufacturing a microcrystalline semiconductor film according to claim 1, wherein the seed crystal comprises a mixed phase grain including both an amorphous region and a crystalline region.
3. The method for manufacturing a microcrystalline semiconductor film according to claim 1, wherein a flow rate of hydrogen is fixed and a flow rate of the deposition gas containing silicon is increased and decreased in the third condition.
4. The method for manufacturing a microcrystalline semiconductor film according to claim 1,
wherein the microcrystalline semiconductor film comprises a crystal grain,
wherein the crystal grain projects from a surface of the microcrystalline semiconductor film,
wherein the microcrystalline semiconductor film has a thickness of more than or equal to 70 nm and less than or equal to 100 nm,
wherein the crystal grain has an orientation plane, and
wherein the crystal grain comprises a crystallite having a size of 13 nm or more.
5. The method for manufacturing a microcrystalline semiconductor film according to claim 1, wherein the microcrystalline semiconductor film has a film density of higher than or equal to 2.25. gcm3 and lower than or equal to 2.35 gcm3.
6. The method for manufacturing a microcrystalline semiconductor film according to claim 1, wherein a rare gas is contained in the deposition gas.
7. A method for manufacturing a semiconductor device by using the method for manufacturing a microcrystalline semiconductor film according to claim 1.
8. A method for manufacturing a semiconductor device, comprising the steps of:
forming a gate electrode over a substrate;
forming a gate insulating film over the gate electrode;
forming a seed crystal over the gate insulating film under a first condition;
forming a first microcrystalline semiconductor film on the seed crystal under a second condition;
forming a second microcrystalline semiconductor film on the first microcrystalline semiconductor film under a third condition;
forming a semiconductor film comprising a microcrystalline semiconductor region and an amorphous semiconductor region over the second microcrystalline semiconductor film;
forming a first impurity semiconductor film over the semiconductor film;
forming an island-shaped second impurity semiconductor film by etching part of the first impurity semiconductor film;
forming an island-shaped first semiconductor stacked body by etching part of the seed crystal, part of the first microcrystalline semiconductor film, part of the second microcrystalline semiconductor film, and part of the semiconductor film;
forming a wiring over the island-shaped second impurity semiconductor film; and
forming a pair of impurity semiconductor films by etching the island-shaped second impurity semiconductor film,
wherein the first condition is a condition that a deposition gas containing silicon is diluted by setting a flow rate of hydrogen to more than or equal to 50 times and less than or equal to 1000 times that of the deposition gas, and a pressure in a process chamber is higher than or equal to 67 Pa and lower than or equal to 50000 Pa,
wherein the second condition is a condition that a deposition gas containing silicon is diluted by setting a flow rate of hydrogen to more than or equal to 100 times and less than or equal to 2000 times that of the deposition gas, and a pressure in the process chamber is higher than or equal to 1333 Pa and lower than or equal to 50000 Pa, and
wherein the third condition is a condition that a pressure in the process chamber is higher than or equal to 1333 Pa and lower than or equal to 50000 Pa, and a first period in which microcrystalline semiconductor is deposited and a second period which is longer than the first period and in which an amorphous semiconductor region formed in the first period is selectively etched are alternately performed.
9. The method for manufacturing a semiconductor device according to claim 8, further comprising the step of forming an insulating region on a side surface of the island-shaped first semiconductor stacked body by exposing the side surface of the island-shaped first semiconductor stacked body to plasma, after the step of forming the island-shaped first semiconductor stacked body and before the step of forming the wiring.
10. The method for manufacturing a semiconductor device according to claim 8, wherein the seed crystal comprises a mixed phase grain including both. an amorphous region and a crystalline region.
11. The method for manufacturing a semiconductor device according to claim 8, wherein a flow rate of hydrogen is fixed and a flow rate of the deposition gas containing silicon is increased and decreased in the third condition.
12. The method for manufacturing a semiconductor device according to claim 8, wherein a rare gas is contained in the deposition gas.
13. The method for manufacturing a semiconductor device according to claim 8, further comprising the steps of:
forming a second semiconductor stacked body in which a microcrystalline semiconductor region and a pair of amorphous semiconductor regions are stacked, by etching part of the island-shaped first semiconductor stacked body;
forming an insulating film over the wiring, the pair of impurity semiconductor films, the second semiconductor stacked body, and the gate insulating film; and
forming a back gate electrode and a pixel electrode over the insulating film.
14. The method for manufacturing a semiconductor device according to claim 13, wherein the gate electrode and the back gate electrode are provided substantially parallel to each other.
15. The method for manufacturing a semiconductor device according to claim 13, wherein the gate electrode and the back gate electrode are electrically connected to each other.
16. The method for manufacturing a semiconductor device according to claim 13, wherein the back gate electrode is in a floating state.
17. The method for manufacturing a semiconductor device according to claim 13, wherein the back gate electrode and the pixel electrode are formed at a same time.
18. A microcrystalline semiconductor film comprising a crystal grain,
wherein the crystal grain projects from a surface of the microcrystalline semiconductor film,
wherein the microcrystalline semiconductor film has a thickness of more than or equal to 70 nm and less than or equal to 100 nm,
wherein the crystal grain has an orientation plane, and
wherein the crystal grain comprises a crystallite having a size of 13 nm or more.
19. The microcrystalline semiconductor film according to claim 18, wherein the microcrystalline semiconductor film has a film density of higher than or equal to 2.25 gcm3 and lower than or equal to 2.35 gcm3.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A system for making real-time predictions about power usage efficiency (PUE) of an electrical system, comprising:
a data acquisition component communicatively connected to a sensor configured to acquire real-time data output from the electrical system;
an analytics server communicatively connected to the data acquisition component, comprising:
a virtual system modeling engine configured to generate predicted data output for the electrical system using a virtual system model of the electrical system,
an analytics engine configured to monitor the real-time data output and the predicted data output of the electrical system, and
a PUE simulation engine configured to use the virtual system model updated based on the real-time data to forecast the PUE.
2. The system for making real-time predictions about PUE of an electrical system, as recited in claim 1, further comprising a client terminal communicatively connected to the analytics server and configured to communicate the forecasted PUE.
3. The system for making real-time predictions about PUE of an electrical system, as recited in claim 1, wherein the forecasted PUE is communicated by way of graphics on a display interfaced with the client terminal.
4. The system for making real-time predictions about PUE of an electrical system, as recited in claim 1, wherein the forecasted PUE is communicated by way of text on a display interfaced with the client terminal.
5. The system for making real-time predictions about PUE of an electrical system, as recited in claim 1, wherein the forecasted PUE is communicated by way of synthesized speech generated by the client terminal.
6. The system for making real-time predictions about PUE of an electrical system, as recited in claim 1, wherein the forecasted PUE is communicated by way of a paper report generated by a printing device interfaced with the client terminal.
7. The system for making real-time predictions about PUE of an electrical system, as recited in claim 1, wherein the PUE simulation engine is further configured to use the virtual system model updated based on the real-time data to forecast data center infrastructure efficiency (DCiE).
comprising a client terminal communicatively connected to the analytics server and configured to communicate the forecasted PUE
8. The system for making real-time predictions about PUE of an electrical system, as recited in claim 1, wherein the analytics server is configured to:
create a base-line PUE model of the electrical system; and
calculate the PUE of the electrical system using the base-line PUE model.
9. The system for making real-time predictions about PUE of an electrical system, as recited in claim 8, wherein the analytics server is further configured to:
create a calibrated PUE model of the electrical system; and
calculate the PUE of the electrical system using the calibrated PUE model.
10. The system for making real-time predictions about PUE of an electrical system, as recited in claim 9, wherein the analytics server is further configured to:
compare the PUE calculated from the calibrated PUE model with the PUE calculated from the base-line PUE model to validate the base-line model.
11. The system for making real-time predictions about PUE of an electrical system, as recited in claim 10, wherein the PUE values from the calibrated model and base-line model are within a predetermined range.
12. The system for making real-time predictions about PUE of an electrical system, as recited in claim 10, wherein the analytics server is further configured to:
update the calibrated PUE model with a first modification to the electrical system; and
calculate the PUE of the electrical system using the updated calibrated PUE model.
13. The system for making real-time predictions about PUE of an electrical system, as recited in claim 12, wherein the analytics server is further configured to:
update the calibrated PUE model with a second modification to the electrical system; and
calculate the PUE of the electrical system using the updated calibrated PUE model.
14. A system for making real-time predictions about data center infrastructure efficiency (DCiE) of an electrical system, comprising:
a data acquisition component communicatively connected to a sensor configured to acquire real-time data output from the electrical system;
an analytics server communicatively connected to the data acquisition component, comprising:
a virtual system modeling engine configured to generate predicted data output for the electrical system using a virtual system model of the electrical system,
an analytics engine configured to monitor the real-time data output and the predicted data output of the electrical system, and
a DCiE simulation engine configured to use the virtual system model updated based on the real-time data to forecast the DCiE.
15. The system for making real-time predictions about DCiE of an electrical system, as recited in claim 14, further comprising a client terminal communicatively connected to the analytics server and configured to communicate the forecasted DCiE.
16. The system for making real-time predictions about DCiE of an electrical system, as recited in claim 14, wherein the forecasted DCiE is communicated by way of graphics on a display interfaced with the client terminal.
17. The system for making real-time predictions about DCiE of an electrical system, as recited in claim 14, wherein the forecasted DCiE is communicated by way of text on a display interfaced with the client terminal.
18. The system for making real-time predictions about DCiE of an electrical system, as recited in claim 14, wherein the analytics server is configured to:
create a base-line DCiE model of the electrical system; and
calculate the DCiE of the electrical system using the base-line DCiE model.
19. The system for making real-time predictions about DCiE of an electrical system, as recited in claim 18, wherein the analytics server is further configured to:
create a calibrated DCiE model of the electrical system; and
calculate the DCiE of the electrical system using the calibrated DCiE model.
20. The system for making real-time predictions about DCiE of an electrical system, as recited in claim 19, wherein the analytics server is further configured to:
compare the DCiE calculated from the calibrated DCiE model with the DCiE calculated from the base-line DCiE model to validate the base-line model.
21. The system for making real-time predictions about DCiE of an electrical system, as recited in claim 20, wherein the DCiE values from the calibrated model and base-line model are within a predetermined range.
22. The system for making real-time predictions about DCiE of an electrical system, as recited in claim 20, wherein the analytics server is further configured to:
update the calibrated DCiE model with a first modification to the electrical system; and
calculate the DCiE of the electrical system using the updated calibrated DCiE model.
23. The system for making real-time predictions about DCiE of an electrical system, as recited in claim 22, wherein the analytics server is further configured to:
update the calibrated DCiE model with a second modification to the electrical system; and
calculate the DCiE of the electrical system using the updated calibrated DCiE model.
24. A computer-readable medium having instructions thereon, that when executed, cause a computer to perform a method comprising:
creating a base-line PUE model of the electrical system; and
calculating the PUE of the electrical system using the base-line PUE model.
25. The computer-readable medium of claim 24, wherein the instructions further cause a computer to perform the method comprising:
creating a calibrated PULE model of the electrical system; and
calculating the PUE of the electrical system using the calibrated PUE model.
26. The computer-readable medium of claim 25, wherein the instructions further cause a computer to perform the method comprising:
validating the base-line PUE model;
updating the calibrated PUE model with a modification to the electrical system; and
calculating the PUE of the electrical system using the updated calibrated PUE model.