1. A method of reading a memory cell, comprising:
applying a potential difference (VDIFF) to a selected memory cell by providing a column potential (VC) on a column line and a row potential (VR) on a row line;
increasing VDIFF by an increment less than a transistor threshold voltage (VT); and
determining whether the increased VDIFF results in a current flow on the column line for the selected memory cell.
2. The method of claim 1, wherein applying a potential difference (VDIFF) to a selected memory cell includes applying VC and VR across a resistive load inverter in the selected memory cell.
3. The method of claim 2, wherein applying VC and VR across a resistive load inverter includes:
applying VC and VR across an NMOS resistive load inverter; and
increasing VDIFF by an increment less than a transistor threshold voltage (VT), including:
maintaining a constant VC; and
decreasing VR by an increment less than an NMOS transistor threshold voltage (VTN).
4. The method of claim 1, wherein increasing VDIFF by an increment less than a transistor threshold voltage VT includes decreasing VR by an increment less than a transistor threshold voltage VT.
5. A method of writing a memory cell, comprising:
applying a potential difference (VDIFF) to a selected memory cell by providing a column potential (VC) on a column line and a row potential (VR) on a row line; and
increasing VDIFF by an increment more than a transistor threshold voltage (VT) to set the selected memory cell to a one state.
6. The method of claim 5, wherein applying a potential difference (VDIFF) to a selected memory cell includes applying VC and VR across a resistive load inverter in the selected memory cell.
7. The method of claim 6, wherein applying VC and VR across a resistive load inverter includes:
applying VC and VR across an NMOS resistive load inverter; and
increasing VDIFF by an increment more than a transistor threshold voltage (VT), including:
maintaining a constant VC; and
decreasing VR by an increment more than an NMOS transistor threshold voltage (VTN).
8. The method of claim 5, wherein increasing VDIFF by an increment more than a transistor threshold voltage VT includes decreasing VR by an increment more than a transistor threshold voltage VT.
9. The method of claim 5, wherein decreasing VDIFF by an increment more than VT resets the selected memory cell to a zero state.
10. The method of claim 9, wherein decreasing VDIFF by an increment more than VT to reset the selected memory cell includes increasing VR by an increment more than VT.
11. A method of operating a memory array, comprising:
applying a potential difference (VDIFF) to each of a plurality of memory cells by providing a column potential (VC) on a column line and a row potential (VR) on a row line;
resetting a first selected memory cell to a zero state by decreasing VDIFF by an increment more than a transistor threshold voltage (VT) to reset the selected memory cell to a zero state;
writing a second selected memory cell to a one state by increasing VDIFF by an increment more than VT to set the selected memory cell to the one state; and
reading a third selected memory cell by:
increasing VDIFF by an increment less than VT; and
determining whether the increased VDIFF results in a current flow on the column line for the selected memory cell.
12. The method of claim 11, wherein applying a potential difference (VDIFF) in each of a plurality of memory cells includes applying VC and VR across a resistive load inverter in each of the plurality of memory cells.
13. The method of claim 12, wherein:
applying VC and VR across a resistive load inverter includes applying VC and VR across an NMOS resistive load inverter; and
writing a second selected memory cell by increasing VDIFF by an increment more than a transistor threshold voltage (VT) includes:
maintaining a constant VC; and
decreasing VR by an increment more than an NMOS transistor threshold voltage (VTN).
14. The method of claim 11, wherein writing a second selected memory cell by increasing VDIFF by an increment more than a transistor threshold voltage VT includes decreasing VR by an increment more than a transistor threshold voltage VT.
15. The method of claim 11, wherein resetting a first selected memory cell includes resetting a row of cells by adjusting VR by an increment larger than VT.
16. The method of claim 11, wherein writing a second selected memory cell to a one state by increasing VDIFF by an increment more than VT includes:
adjusting VR for a write operation by an increment greater than a transistor threshold voltage to turn a first transistor on for cells within a selected row; and
adjusting a second column potential VC on a second column line by an amount to prevent a second transistor in the selected row from turning on in response to adjusting the row potential for the write operation.
17. The method of claim 11, wherein reading a third selected memory cell includes:
decreasing VR by an increment less than a transistor threshold voltage increment; and
determining if the decreased VR results in a current flow on a corresponding column line for the memory cell.
18. A method of forming a SRAM circuit, comprising:
providing a memory array, a controller, a row line voltage generator, a column line voltage generator, and a column line current detector;
coupling the controller to the row line voltage generator, the column line voltage generator, and the column line current detector;
coupling the row line voltage generator to row lines within the memory array such that the controller is able to vary a potential on a selected row line;
coupling the column line voltage generator to column lines within the memory array such that the controller is able to vary a potential on one or more selected column lines; and
coupling the column line current detector to the column lines within the memory array such that the controller is able to determine current flow on a selected column line.
19. The method of claim 18, wherein providing a memory array includes providing a plurality of memory cells, each cell being provided by:
forming a PMOS transistor with a gate;
forming an NMOS transistor with a gate;
coupling the PMOS transistor gate in series with the NMOS transistor; and
coupling the NMOS transistor gate in series with the PMOS transistor.
20. The method of claim 19, wherein forming a PMOS transistor with a gate and forming an NMOS transistor with a gate includes forming a lightly doped polysilicon gate for both the PMOS transistor and the NMOS transistor.
21. The method of claim 19, further including:
coupling the PMOS transistor and the NMOS transistor gate between a PWRP power supply and a first reference line; and
coupling the NMOS transistor and the PMOS transistor gate between a PWRN power supply and a second reference line.
22. The method of claim 19, further including:
coupling the PMOS transistor and the NMOS transistor gate between a constant power supply and a ground reference line; and
coupling the NMOS transistor and the PMOS transistor gate between a column line with an adjustable potential and a row line with an adjustable potential.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A processing-target image creating device configured to create a processing-target image subjected to an image conversion process for obtaining an output image based on a plurality of input images captured by a plurality of cameras, comprising;
a coordinates-associating part configured to associate coordinates on each input image plane on which each input image is positioned, coordinates on a space model onto which each input image is projected, and coordinates on a processing-target image plane on which the processing-target image is positioned and onto which an image projected on the space model is re-projected;
an image adjusting part configured to adjust the processing-target image by determining for each input image a slope of a straight line joining a coordinate on the space model and a coordinate on the processing-target image plane corresponding to the coordinate on the space model,
wherein the coordinates-associating part associates the coordinate on the space model with the coordinate on the processing-target image plane such that each of the straight lines relating to one input image becomes parallel to one another on a plane perpendicular to the processing-target image plane, or associates the coordinate on the space model with the coordinate on the processing-target image plane such that each of the straight lines relating to one input image passes through a single predetermined point, and
wherein the image adjusting part determines for each input image slopes of the straight lines such that each coordinate on the processing-target image plane corresponding to an image representing a predetermined feature in each input image corresponds with one another on a dividing line between image parts corresponding to each input image on the processing-target image plane.
2. The processing-target image creating device as claimed in claim 1,
wherein a distance between each coordinate on the processing-target image plane corresponding to an image representing a predetermined feature in each input image on the processing-target image plane and a re-projection axis of the space model is set adjustably.
3. The processing-target image creating device as claimed in claim 1,
wherein the plurality of cameras are installed at different heights.
4. The processing-target image creating device as claimed in claim 1,
wherein a predetermined feature in each input image is an infinity line viewed from each camera.
5. A processing-target image creating method of creating a processing-target image subjected to an image conversion process for obtaining an output image based on a plurality of input images captured by a plurality of cameras, comprising:
a coordinates-associating step of associating coordinates on each input image plane on which each input image is positioned, coordinates on a space model onto which each input image is projected, and coordinates on a processing-target image plane on which the processing-target image is positioned and onto which an image projected on the space model is re-projected;
an image adjusting step of adjusting the processing-target image by determining for each input image a slope of a straight line joining a coordinate on the space model and a coordinate on the processing-target image plane corresponding to the coordinate on the space model,
wherein, in the coordinates-associating step, the coordinate on the processing-target image plane is associated with the coordinate on the space model such that each of the straight lines relating to one input image becomes parallel to one another on a plane perpendicular to the processing-target image plane, or the coordinate on the processing-target image plane is associated with the coordinate on the space model such that each of the straight lines relating to one input image passes through a single predetermined point, and
wherein, in the image adjusting step, slopes of the straight lines are determined for each input image such that each coordinate on the processing-target image plane corresponding to an image representing a predetermined feature in each input image corresponds with one another on a dividing line between image parts corresponding to each input image on the processing-target image plane.
6. An operation assisting system configured to assist a travel or an operation of an operated body, comprising:
the processing-target image creating device claimed in claim 1; and
a display part installed in an operation room for moving or operating the operated body, and configured to display an output image created based on a processing-target image created by the processing-target image creating device.