1. A sizing support system for supporting a computer sizing having n level hierarchical resources, comprising:
a memory;
a table definition module; and
a field calculation module,
wherein the memory stores:
a lower level resource data indicating a possible kind and a maximum number of lower level resources for each resource belonging to the hierarchical resources; and
a resource data indicating a parameter of each resource belonging to the hierarchical resources, a processing levels of resources to be processed includes:
a K th level (K is an integer of 1 to n-2) constituted by first resource group;
a K+1 th level constituted by second resource group; and
a K+2 th level constituted by third resource group,
the table definition module is configured to generate a table frame indicating a configuration of resource belonging to the first resource group by referring to the lower level resource data, in a unit process applied to the processing levels; and
the field calculation module is configured to calculate a feature value of the configuration by referring to the table frame and the resource data.
2. The sizing support system according to claim 1,
wherein the resource data includes scalability data indicating a scalability of each resource belonging to the hierarchical resources, and
the field calculation module calculates a performance of a resource having the configuration indicated in the table frame by referring the scalability data.
3. The sizing support system according to claim 1,
wherein the field calculation module includes a scale estimation module,
the resource data includes scalability data indicating a scalability of each resource belonging to the hierarchical resources,
the scale estimation module generates a scale table indicating a performance magnification calculated for the each configuration by referring the scalability data, and
the performance magnification is a ratio of a performance of a certain resource to a performance of the certain resource when the certain resource has only one 1 rank lower level resource.
4. The sizing support system according to claim 3,
wherein the number of element resources of the second resource group is i,
the scalability data of the second resource group is represented by an array sK+1 i,
the number of element resources of the third resource group is j,
the scalability data of the third resource group is represented by an array sK+2 j, and
the scale estimation module calculates the performance magnification indicated by using a following equation,
Sij=sK+1i\xd7i\xd7sK+2j\xd7j.
5. The sizing support system according to claim 3,
wherein the field calculation module further includes a performance estimation module,
the resource data includes a unit performance data indicating a unit performance of a resource of the third resource group, and
the performance estimation module generates a performance table indicating a performance of the each configuration by multiplying the performance magnification indicated in the scale table and the unit performance indicated in the unit performance data.
6. The sizing support system according to claim 5,
wherein the field calculation module further includes a cost estimation module,
the resource data includes a cost data indicating a cost of each resource of the hierarchical resources, and
the cost estimation module generates a cost table indicating a cost calculated for the each configuration by referring the cost data.
7. The sizing support system according to claim 5,
wherein the memory stores a cost table indicating a cost of the each configuration.
8. The sizing support system according to claim 6, further comprising a processing level update module configured to initialize the K to n-2,
the processing level update module decrements the K when the unit process is finished, and extracts both the unit performance data and the cost data of the third resource group to be used in a following unit process by referring the performance table and the cost table, and
the table definition module and the field calculation module repeatedly execute the unit process for the processing levels corresponding to the every K.
9. The sizing support system according to claim 7, further comprising a processing level update module configured to initialize the K to n-2,
the processing level update module decrements the K when the unit process is finished, and extracts the unit performance data of the third resource group to be used in a following unit process by referring the performance table, and
the table definition module and the field calculation module repeatedly execute the unit process for the processing levels corresponding to the every K.
10. The sizing support system according to claim 8, further comprising a display configured to display at least one of the scale table, the performance table and the cost table, in a case that the unit process is finished when the K is 1.
11. The sizing support system according to claim 8, further comprising:
a user view generating module; and
a display,
wherein the user view generating module makes a correlation of at least two of the scale table, the performance table and the cost table in a case that the unit process is finished when the K is 1, and generates a user view data indicating the correlation, and
the display displays the user view data.
12. The sizing support system according to claim 11,
wherein the user view data indicates a relation between a performance indicated in the performance table and a cost indicated in the cost table, and
the display displays the relation for the each configuration.
13. A sizing support system for supporting a computer sizing of hierarchical resources, comprising:
a memory storing user view data indicating a relation between a performance and a cost for each configuration of the hierarchical resources; and
a display configured to display the user view data.
14. A sizing support method for supporting a computer sizing having n level hierarchical resources, comprising:
(A) a computer storing a lower level resource data indicating a possible kind and a maximum number of lower level resources for each resource belonging to the hierarchical resources into the memory;
(B) the computer storing a resource data indicating a parameter of each resource belonging to the hierarchical resources,
(C) the computer setting a processing level; and
(D) computer executing a unit processing for the processing level,
wherein (c) the setting includes:
(a) a K th level (K is an integer of 1 to n-2) constituted by first resource group;
(b) a K+1 th level constituted by second resource group; and
(c) a K+2 th level constituted by third resource group, and
the (D) includes:
(a) generating a table frame indicating a configuration of resource belonging to the first resource group by referring to the lower level resource data stored in the memory; and
(b) calculating a feature value of the configuration by referring to the resource data stored in the memory.
15. The sizing support method according to claim 14,
wherein the resource data includes scalability data indicating a scalability of each resource belonging to the hierarchical resources, and
said (b) calculating includes calculating a performance of a resource having the configuration indicated in the table frame by referring the scalability data.
16. The sizing support method according to claim 14,
wherein the resource data includes scalability data indicating a scalability of each resource belonging to the hierarchical resources,
said (b) calculating includes:
(b1) generating a scale table indicating a performance magnification calculated for the each configuration by referring the scalability data, and
the performance magnification is a ratio of a performance of a certain resource to a performance of the certain resource when the certain resource has only one 1 rank lower level resource.
17. The sizing support method according to claim 16, wherein the number of element resources of the second resource group is i,
the scalability data of the second resource group is represented by an array sK+1 i,
the number of element resources of the third resource group is j,
the scalability data of the third resource group is represented by an array SK+2 j, and
in said (b1) generating, the performance magnification indicated is calculated by using a following equation,
Sij=sK+1i\xd7i\xd7sK+2j\xd7j.
18. The sizing support method according to claim 16,
wherein the resource data includes a unit performance data indicating a unit performance of a resource of the third resource group, and
said (b) calculating includes:
(b2) generating a performance table indicating a performance of the each configuration by multiplying the performance magnification indicated in the scale table and the unit performance indicated in the unit performance data.
19. The sizing support method according to claim 18,
wherein the resource data includes a cost data indicating a cost of each resource of the hierarchical resources, and
said (b) calculating includes:
(b3) generating a cost table indicating a cost calculated for the each configuration by referring the cost data.
20. The sizing support method according to claim 19, further comprising:
(E) the computer initializing the K to n-2;
(F) the computer decrementing the K when said (E) initializing is finished and extracting both the unit performance data and the cost data of the third resource group to be used in a following unit process by referring the performance table and the cost table; and
(G) the computer executing repeatedly the unit process for the processing levels corresponding to every K.
21. The sizing support method according to claim 20, further comprising:
(H) displaying at least one of the scale table, the performance table and the cost table, in a case that the unit process is finished when the K is 1.
22. The sizing support method according to claim 20, further comprising:
(I) making a correlation of at least two of the scale table, the performance table and the cost table in a case that the unit process is finished when the K is 1, and generates a user view data indicating the correlation, and
(J) computer displaying the user view data on a display.
23. The sizing support method according to claim 22,
wherein the user view data indicates a relation between a performance indicated in the performance table and a cost indicated in the cost table, and
the relation for the each configuration is displayed on the display in said (J) displaying.
24. A sizing support method for supporting a computer sizing of hierarchical resources, comprising:
(A) computer generating user view data indicating a relation between a performance and a cost for each configuration of the hierarchical resources; and
(B) displaying the user view data.
25. A computer-readable software product for realizing a data sizing support method for supporting a computer sizing having n level hierarchical resources, wherein the method comprises:
(A) a computer storing a lower level resource data indicating a possible kind and a maximum number of lower level resources for each resource belonging to the hierarchical resources into the memory;
(B) the computer storing a resource data indicating a parameter of each resource belonging to the hierarchical resources,
(C) the computer setting a processing level; and
(D) computer executing a unit processing for the processing level,
wherein (c) the setting includes:
(a) a K th level (K is an integer of 1 to n-2) constituted by first resource group;
(b) a K+1 th level constituted by second resource group; and
(c) a K+2 th level constituted by third resource group, and
the (D) includes:
(a) generating a table frame indicating a configuration of resource belonging to the first resource group by referring to the lower level resource data stored in the memory; and
(b) calculating a feature value of the configuration by referring to the resource data stored in the memory.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1-31. (canceled)
32. A method for fabricating a ferroelectric memory device comprising the steps of:
forming a lower insulation layer on a semiconductor substrate;
forming ferroelectric capacitors in rows and columns on the lower insulation layer;
forming conductive patterns, each electrically connected to a plurality of the ferroelectric capacitors that are adjacent along a row;
forming an upper insulation layer on the semiconductor substrate, wherein the upper insulating layer includes via holes; and
forming columns of plate lines, wherein each of the plate lines is electrically connected through the via holes in the upper insulation layer to the conductive patterns, and wherein at least two of the plate lines are on each of the conductive patterns.
33. The method of claim 32, wherein forming conductive patterns comprises:
forming a supporting insulation layer on the lower insulation layer that covers the ferroelectric capacitors;
planarizing the supporting insulation layer to expose a top of the ferroelectric capacitors;
forming a conductive layer on the supporting insulation layer and the top of the ferroelectric capacitors; and
patterning the conductive layer to form the conductive patterns.
34. The method of claim 32, wherein forming conductive patterns comprises:
forming an insulation layer on the lower insulation layer covering the ferroelectric capacitors;
patterning the insulating layer to forming contact holes that expose the ferroelectric capacitors;
forming a conductive layer on the insulation layer and in the contact holes; and patterning the conductive layer to form conductive patterns.
35. The method of claim 32, wherein:
each of the conductive patterns is electrically connected to 4*2 ferroelectric capacitors arranged in two rows and four columns;
two of the plate lines are on each of the conductive patterns;
the plate lines in odd numbered columns are electrically connected to the conductive patterns in odd numbered rows; and
the plate lines in even numbered columns are electrically connected to the conductive patterns in even numbered rows.
36. The method of claim 32, wherein:
each of the conductive patterns is electrically connected to a top of four of the ferroelectric capacitors along a row;
four of the plate lines are on each of the conductive patterns; and
the plate lines in the 4*(k\u22121)+i columns are electrically connected to the conductive patterns in the 4*(k\u22121)+i rows, wherein k is natural number and i is in a range from 1 to 4.
37. The method of claim 32, wherein forming the upper insulation layer comprises forming a first and a second upper insulation layer, and further comprising forming a plurality of main word lines on the first upper insulating layer and parallel to the plate lines, wherein the second upper insulating layer is formed on the first upper insulating layer and the plate lines.
38. The method of claim 32, further comprising forming a hydrogen barrier layer on the ferroelectric capacitors.
39. A method for fabricating a ferroelectric memory device comprising the steps of:
forming a lower insulation layer on a semiconductor substrate;
forming a supporting insulation layer on the lower insulation layer;
patterning the supporting insulation layer to form trenches arranged in rows and columns;
forming bottom electrodes in the trenches on the supporting insulation layer;
forming a ferroelectric layer on the bottom electrodes;
forming an upper electrode layer on the ferroelectric layer;
patterning the upper electrode layer to form upper electrodes arranged in rows and columns, and wherein each of the upper electrodes is on at least a row of four adjacent bottom electrodes;
forming an upper insulation layer; and
forming a plurality of columns of plate lines, wherein each of the plate lines is electrically connected to at least one of the upper electrodes through the upper insulation layer, and wherein at least two of the plate lines are on each of the upper electrodes.
40. The method of claim 39, wherein:
each of the upper electrodes is on two rows of four of the bottom electrodes;
two of the plate lines are on each of the upper electrodes;
the plate lines in odd numbered columns are electrically connected to the upper electrodes in odd numbered rows; and
the plate lines in even numbered columns are electrically connected to the upper electrodes in even numbered rows.
41. The method of claim 39, wherein:
each of the upper electrodes is on a row of four of the bottom;
four of the plate lines are on each of the upper electrodes; and
the plate lines in the 4*(k\u22121)+i columns are electrically connected to the upper electrodes in the 4*(k\u22121)+i rows, wherein k is natural number and i is in a range from 1 to 4.