1. A source driver of a display panel, comprising:
a channel state signal generator for generating a first channel state signal that is at a first logic state for a time period depending on an adjustable state length data that is comprised of multiple bits stored into a register; and
a plurality of first switches that are opened for uncoupling channel output signals from source lines of the display panel when the first channel state signal is at the first logic state for charge share of the source lines, wherein the adjustable state length data is not a periodic signal used for generating the channel output signal, and wherein the adjustable state length data is not a periodic signal with pulses used for timing of said charge share,
and wherein the time period during which the first channel state signal is at the first logic state is determined by the state length data, and is independent of time periods during which a load control signal is activated,
and wherein said load control signal is activated during a part or an entirety of a blanking period when image data for determining said channel output signals is not latched by the source driver.
2. The source driver of claim 1, wherein the channel state signal generator generates a second channel state signal that is at a second logic state within the time period when the first channel state signal is at the first logic state.
3. The source driver of claim 2, further comprising:
a plurality of second switches that are closed for coupling together the source lines of the display panel when the second channel state signal is at the second logic state.
4. The source driver of claim 3, wherein the second switches are not closed simultaneously with the first switches being closed.
5. The source driver of claim 3, wherein the channel state signal generator includes:
a register for storing the state length data;
a counter for counting a number of cycles of a clock signal from when the load control signal is activated;
a comparator for activating a reset signal when the state length data and the counted number of cycles of the clock signal are substantially equal; and
an output unit for generating the second channel state signal that is set to the second logic state after the counter begins counting the number of cycles of the clock signal and until an end of activating the reset signal.
6. The source driver of claim 5, wherein the output unit generates the first channel state signal that is set to the first logic state after the load control signal is activated and until after the end of activating the reset signal.
7. The source driver of claim 5, wherein the state length data is provided to the source driver from an external device independent of the load control signal.
8. The source driver of claim 1, further comprising:
a plurality of driving circuits for generating the channel output signals from color image data for the display panel.
9. The source driver of claim 8, wherein the state length data is input as part of at least one color image data during a time when the color image data is not latched by the driving circuits.
10. The source driver of claim 1, wherein the display panel is for a TFT-LCD (Thin Film Transistor-Liquid Crystal Display).
11. A source driver of a display panel, comprising:
means for generating a first channel state signal that is at a first logic state for a time period depending on an adjustable state length data that is comprised of multiple bits stored into a register; and
means for uncoupling channel output signals from source lines of the display panel when the first channel state signal is at the first logic state for charge share of the source lines, wherein the adjustable state length data is not a periodic signal used for generating the channel output signal, and wherein the adjustable state length data is not a periodic signal with pulses used for timing of said charge share,
and wherein the time period during which the first channel state signal is at the first logic state is determined by the state length data, and is independent of time periods during which a load control signal is activated,
and wherein said load control signal is activated during a part or an entirety of a blanking period when image data for determining said channel output signals is not latched by the source driver.
12. The source driver of claim 11, further comprising:
means for setting the first channel state signal to the first logic state for said time period after activation of the load control signal for the display device.
13. The source driver of claim 12, further comprising:
means for inputting the state length data from an external device independent of the load control signal.
14. The source driver of claim 11, further comprising:
means for generating a second channel state signal that is at a second logic state within the time period when the first channel state signal is at the first logic state; and
means for coupling together the source lines of the display panel when the second channel state signal is at the second logic state.
15. The source driver of claim 11, further comprising:
means for generating the channel output signals from image data for the display panel.
16. A method of driving a display panel, comprising:
inputting an adjustable state length data that is comprised of multiple bits and storing said multiple bits into a register;
generating a first channel state signal that is at a first logic state for a time period depending on the state length data; and
uncoupling channel output signals from source lines of the display panel when the first channel state signal is at the first logic state for charge share of the source lines, wherein the adjustable state length data is not a periodic signal used for generating the channel output signal, and wherein the adjustable state length data is not a periodic signal with pulses used for timing of said charge share,
wherein the time period during which the first channel state signal is at the first logic state is determined by the state length data, and is independent of time periods during which a load control signal is activated,
and wherein said load control signal is activated during a part or an entirety of a blanking period when image data for determining said channel output signals is not latched by the source driver.
17. The method of claim 16, further comprising:
generating a second channel state signal that is at a second logic state within the time period when the first channel state signal is at the first logic state; and
coupling together the source lines of the display panel when the second channel state signal is activated at the second logic state.
18. The method of claim 16, further comprising:
setting the first channel state signal to the first logic state after activation of the load control signal; and
inputting the state length data from an external device independent of the load control signal.
19. The method of claim 16, further comprising:
generating the channel output signals from color image data for the display panel; and
inputting the state length data as part of at least one color image data during a time when the color image data is not being latched for generating gray voltages.
20. The method of claim 16, wherein the display panel is for a TFT-LCD (Thin Film Transistor-Liquid Crystal Display).
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. An electronic apparatus, comprising:
a base chassis formed as unitary member, the base chassis including
a bottom face wall extending on a first plane, the bottom face wall having a first mounting face section and a second mounting face section disposed opposite each other,
a peripheral wall, and
a peripheral flange protruding outward from the peripheral wall, being on a second plane that is parallel to the first plane, and extending beyond the bottom face wall;
a display unit including a display panel, the display unit being attached to the first mounting face section of the base chassis and inserted in a mounting recess that is partially enclosed by the bottom face wall and the peripheral wall;
a control circuit board attached to the second mounting face section of the base chassis; and
a rear cover attached to the second mounting face section of the base chassis so as to cover the control circuit board, the rear cover being positioned on the base chassis such that an entire outer perimeter of the rear cover adjacent to the base chassis is disposed within an entire outer perimeter of the peripheral flange.
2. The electronic apparatus according to claim 1, wherein the control circuit board includes a board and a plurality of electronic parts on the board, the plurality of electronic parts including at least one of a CPU (Central Processing Unit) and a chipset.
3. The electronic apparatus according to claim 2, further comprising a medium driving section attached to the second mounting face section of the base chassis.
4. The electronic apparatus according to claim 3, further comprising a cooling fan attached to the second mounting face section of the base chassis.
5. The electronic apparatus according to claim 4, wherein the bottom face wall of the base chassis includes air stream passing holes.
6. The electronic apparatus according to claim 5, wherein the base chassis further includes
speaker arrangement holes, and
speakers inserted into the speaker arrangement holes, and
wherein a thickness of the speakers projects in a forward direction toward the display unit.
7. The electronic apparatus according to claim 1, wherein the display unit further includes a front panel disposed parallel to the display panel.
8. The electronic apparatus according to claim 7, wherein dimensions of an outer perimeter of the front panel corresponds to dimensions of an outer perimeter of the bottom face wall of the base chassis, and
wherein the dimensions of the outer perimeter of the front panel are greater than the dimensions of the outer perimeter of the bottom face wall of the base chassis, such that the front panel disposed encloses the display panel in the mounting recess.
9. The electronic apparatus according to claim 1, wherein the base chassis further includes a reflective lamp section that is a through hole in the peripheral flange, the reflective lamp section adapted to allow passage of light as an indicator of a status of the electronic apparatus.
10. The electronic apparatus according to claim 1, further comprising a holding member attached to an edge of the peripheral flange of the base chassis.
11. The electronic apparatus according to claim 10, wherein the holding member has a U-shaped profile, into which the edge of the peripheral flange of the base chassis is inserted.
12. The electronic apparatus according to claim 10, wherein the holding member secures a placement pad to prevent damage to a base of the electronic apparatus when the electronic apparatus is placed thereon in an upright position on a surface.
13. The electronic apparatus according to claim 10, wherein the holding member includes a through hole into which a placement pad for preventing damage to a base of the electronic apparatus is inserted.
14. The electronic apparatus according to claim 13, wherein the placement pad includes an elongated placement face section from which a held portion protrudes, the held portion including an inserted portion and a constricted portion, and
wherein the through hole of the holding member includes a wide portion into which the inserted portion of the placement pad is inserted and a narrow portion that secures the constricted portion of the placement pad.
15. The electronic apparatus according to claim 14, wherein the edge of the peripheral flange includes a holding recess, and
wherein a location of the holding recess corresponds to a location of the narrow portion of the through hole such that the inserted portion of the held portion is accommodated in the holding recess when the constricted portion of the held portion is secured by the narrow portion of the through hole of the holding member.