1. A method, comprising:
identifying, by a particular node in a directed acyclic graph (DAG) in a computer network, a low-contact node in the DAG;
identifying neighbors of the low-contact node;
establishing a multicast tree from the particular node to the low-contact node through a plurality of the neighbors to reach the low-contact node; and
sending traffic from the particular node to the low-contact node as multicast traffic on the multicast tree, wherein each of the plurality of neighbors attempts to forward the traffic to the low-contact node.
2. The method as in claim 1, wherein the low-contact node is identified as a node that is at risk of having an invalid path when attempts are made to reach the low-contact node.
3. The method as in claim 1, wherein the low-contact node is identified as one of either a node not participating in keep-alive message transmission or a node infrequently transmitting traffic.
4. The method as in claim 1, wherein determining the low-contact node comprises:
receiving an indication from the low-contact node that the low-contact node is a low-contact node.
5. The method as in claim 4, wherein the indication comprises a list of neighbors of the low-contact node, and where identifying the neighbors comprises:
examining the indication from the low-contact node to identify the neighbors of the low-contact node.
6. The method as in claim 1, further comprising:
informing the low-contact node of a multicast group corresponding to the multicast tree.
7. The method as in claim 1, wherein establishing the multicast tree comprises:
ensuring path diversity where available within the DAG.
8. The method as in claim 7, further comprising:
receiving a request from the low-contact node for path diversity within the multicast tree.
9. The method as in claim 1, wherein the particular node is a root node of the DAG.
10. The method as in claim 1, wherein sending comprises sending all traffic to the low-contact node as multicast traffic on the multicast tree.
11. An apparatus, comprising:
one or more network interfaces;
a processor coupled to the network interfaces and adapted to execute one or more processes; and
a memory configured to store a process executable by the processor, the process when executed operable to:
identify a low-contact node in a directed acyclic graph (DAG) in a computer network;
identify neighbors of the low-contact node;
establish a multicast tree to the low-contact node through a plurality of the neighbors to reach the low-contact node; and
send traffic to the low-contact node as multicast traffic on the multicast tree, wherein each of the plurality of neighbors attempts to forward the traffic to the low-contact node.
12. The apparatus as in claim 11, wherein the process when executed is further operable to identify the low-contact node as a node that is at risk of having an invalid path when attempts are made to reach the low-contact node.
13. The apparatus as in claim 11, wherein the process when executed is further operable to identify the low-contact node through receipt of an indication from the low-contact node that the low-contact node is a low-contact node.
14. The apparatus as in claim 13, wherein the indication comprises a list of neighbors of the low-contact node.
15. A method, comprising:
determining, by a node in a directed acyclic graph (DAG) in a computer network, a status of the node as a low-contact node in the DAG;
identifying neighbors of the low-contact node;
transmitting an indication that the node is a low-contact node to a root node of the DAG, the indication having a list of the identified neighbors of the low-contact node; and
receiving traffic from one or more of the neighbors as multicast traffic.
16. The method as in claim 15, wherein the status as the low-contact node is identified based on the node being at risk of having an invalid path when attempts are made to reach the low-contact node.
17. The method as in claim 15, wherein the status as the low-contact node is identified based on the node not participating in keep-alive message transmission.
18. The method as in claim 15, wherein identifying the neighbors comprises:
transmitting a discovery message from the node;
receiving replies from the neighbors; and
identifying the neighbors based on the replies.
19. The method as in claim 15, further comprising:
updating the neighbors based on from which neighbors the multicast traffic is received.
20. The method as in claim 19, wherein updating comprises:
identifying a list of neighbors from which traffic was expected to arrive;
comparing the neighbors from which the traffic is received to the list of expected neighbors;
identifying neighbors within the list from which traffic has not arrived; and
modifying route tables of the low-contact node to remove the neighbors from which traffic has not arrived.
21. The method as in claim 15, further comprising:
requesting, within the indication, path diversity within a multicast tree corresponding to the multicast traffic.
22. The method as in claim 15, further comprising:
receiving identification of a multicast group corresponding to the multicast traffic from the root; and
joining the multicast group by the low-contact node.
23. The method as in claim 15, further comprising:
receiving duplicate multicast traffic from the neighbors; and
in response, ignoring all but a first received multicast traffic.
24. The method as in claim 15, wherein the low-contact node is a wireless node.
25. The method as in claim 15, wherein receiving traffic from one or more of the neighbors as multicast traffic comprises one of either:
receiving traffic from one or more of the neighbors as a multicast packet from each of the one or more of the neighbors; or
receiving traffic from one or more of the neighbors as a unicast packet decapsulated from multicast traffic from each of the one or more of the neighbors.
26. An apparatus, comprising:
one or more network interfaces adapted to communicate in a directed acyclic graph (DAG) in a computer network;
a processor coupled to the network interfaces and adapted to execute one or more processes; and
a memory configured to store a process executable by the processor, the process when executed operable to:
determine a status of the apparatus as a low-contact node in the DAG;
identify neighbors of the low-contact node;
transmit an indication that the apparatus is a low-contact node to a root node of the DAG, the indication having a list of the identified neighbors of the low-contact node; and
receive traffic from one or more of the neighbors as multicast traffic.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A method of designing a semiconductor circuit, the semiconductor circuit comprising
an array of repeating blocks, each of the blocks comprising a device, and
at least one signal line connecting the devices of the blocks,
said method performed by at least one processor and comprising:
generating a model of the semiconductor circuit, the model comprising
a functional area corresponding to at least one first block among the blocks of the array, and
a loading area corresponding to at least one second block among the blocks of the array;
extracting, in the functional area, parasitic parameters of the at least one signal line and the device of the at least one first block; and
extracting, in the loading area, parasitic parameters of the at least one signal line, without extracting parasitic parameters of the device of the at least one second block.
2. The method of claim 1, further comprising:
generating a netlist of the semiconductor circuit, the netlist comprising the parasitic parameters extracted from the functional area and the loading area.
3. The method of claim 1, wherein the at least one signal line extends through the at least one second block.
4. The method of claim 3, further comprising:
specifying first and second pins for the at least one second block, the first and second pins corresponding to connections points of the at least one second block to other blocks via the at least one signal line, and
specifying a direction of current along the at least one signal line between the first and second pins in the at least one second block,
wherein said extracting the parasitic parameters of the at least one signal line in the loading area comprises using the specified direction of current between the first and second pins in the at least one second block.
5. The method of claim 4, further comprising:
generating a netlist of the semiconductor circuit, the netlist comprising the parasitic parameters extracted from the functional area and the loading area and the first and second pins.
6. The method of claim 4, wherein the at least one signal line further extends through the at least one first block.
7. The method of claim 6, further comprising:
specifying third and fourth pins for the at least one first block, the third and fourth pins corresponding to connections points of the at least one first block to other blocks via the at least one signal line, and
specifying a direction of current along the at least one signal line between the third and fourth pins in the at least one first block,
wherein said extracting the parasitic parameters in the functional area comprises using the specified direction of current between the third and fourth pins in the at least one first block.
8. The method of claim 1, wherein
the at least one first block comprises multiple first blocks,
the at least one second block is positioned between the first blocks, and
the at least one signal line extends through the at least one second block to connect the first blocks.
9. The method of claim 8, wherein
the array comprises a one-dimensional array, and
the first blocks are arranged at opposite ends of the one-dimensional array.
10. The method of claim 9, wherein
the semiconductor circuit comprises a memory circuit,
the blocks in the one-dimensional array comprise at least one selected from the group consisting of input-output (IO) blocks and decoder blocks, and
the at least one signal line comprises at least one selected from the group consisting of at least one power line and at least one control line.
11. The method of claim 8, wherein
the array comprises a two-dimensional array,
the first blocks are arranged at corners of the two-dimensional array, and
the at least one second block comprises multiple second blocks arranged along fours sides of the two-dimensional array and between the first blocks.
12. The method of claim 11, wherein the model further comprises an empty area surrounded by the first and second blocks arranged at the corners and along the four sides of the array.
13. The method of claim 11, wherein
the semiconductor circuit comprises a memory circuit,
the blocks in the two-dimensional array comprises memory blocks, and
the at least one signal line comprises at least one selected from the group consisting of at least one word line, at least one bit line, and at least one power line.
14. The method of claim 1, further comprising:
performing a simulation of an operation of the semiconductor circuit, wherein the simulation comprises using the extracted parasitic parameters.
15. A memory compiler, comprising a processor configured to:
generate a model of a memory circuit, the model comprising
at least one signal line selected from the group consisting of at least one word line, at least one bit line, at least one control line, and at least one power line, and
a plurality of blocks connected in series by the at least one signal line, the at least one signal line extending through at least one of the blocks of the plurality of blocks, each of the blocks of the plurality of blocks selected from the group consisting of a memory block, a decoder block, an input-output (IO) block, and a control block;
specify first and second pins for the at least one block through which the at least one signal line extends, the first and second pins corresponding to connections points of the at least one block to other blocks via the at least one signal line;
specify a direction of current along the at least one signal line between the first and second pins in the at least one block; and
extract parasitic parameters of the plurality of blocks, wherein the processor is configured to extract the parasitic parameters of the at least one block using the specified direction of current between the first and second pins.
16. The memory compiler of claim 15, wherein the processor is further configured to generate a netlist of the memory circuit, the netlist comprising the extracted parasitic parameters of the blocks of the plurality of blocks.
17. The memory compiler of claim 15, wherein
each of the blocks of the plurality of blocks comprises a device connected to the at least one signal line, and
the blocks of the plurality of blocks comprise
at least one functional block in which the processor is configured to extract the parasitic parameters of the corresponding device and the at least one signal line, and
at least one loading block in which the processor is configured to extract the parasitic parameters of the at least one signal line, without extracting parasitic parameters of the corresponding device.
18. The memory compiler of claim 17, wherein the model of the memory circuit comprises
a two-dimensional array of repeating memory blocks arranged in a plurality of rows and columns, wherein the memory blocks in each of the rows are connected by word lines, and the memory blocks in each of the columns are connected by bit lines,
a column of repeating decoder blocks, each of the decoder blocks connected to one of the rows of memory blocks by the corresponding word lines, wherein the decoder blocks are connected by control lines,
a row of repeating IO blocks, each of the IO blocks connected to one of the columns of memory blocks by the corresponding bit lines, wherein the IO blocks are connected by further control lines, and
a control block connected to the column of decoder blocks and the row of IO blocks by the corresponding control lines.
19. The memory compiler of claim 17, wherein
the two-dimensional array of memory blocks comprises:
functional memory blocks at four corners of the two-dimensional array, and
loading memory blocks arranged along fours sides of the two-dimensional array between the functional memory blocks,
the column of decoder blocks comprises:
functional decoder blocks corresponding to uppermost and lowermost rows in the two-dimensional array of memory blocks, and
loading decoder blocks corresponding to the remaining rows in the two-dimensional array of memory blocks, and
the row of IO blocks comprises:
functional IO blocks corresponding to leftmost and rightmost columns in the two-dimensional array of memory blocks, and
loading IO blocks corresponding to the remaining columns in the two-dimensional array of memory blocks.
20. A computer program product, comprising a non-transitory, computer-readable medium containing instructions therein which, when executed by at least one processor, cause the at least one processor to
generate a model of a semiconductor circuit, the model comprising
at least one signal line, and
a plurality of repeating blocks connected in series by the at least one signal line, wherein
each of the blocks of the plurality of repeating blocks comprises a device connected to the at least one signal line,
the blocks of the plurality of repeating blocks comprise loading blocks arranged between functional blocks, and
the at least one signal line extends through the loading blocks to connect the functional blocks;
specify, for each of the loading blocks, first and second pins corresponding to connections points of the loading block to other blocks of the plurality of repeating blocks via the at least one signal line;
specify, for each of the loading blocks, a direction of current along the at least one signal line between the corresponding first and second pins;
extract, in each of the functional blocks, parasitic parameters of the corresponding device and the at least one signal line; and
extract, in each of the loading blocks, parasitic parameters of the at least one signal line, without extracting parasitic parameters of the corresponding device, wherein the parasitic parameters of the at least one signal line are extracted using the specified direction of current between the corresponding first and second pins.