1. A single-poly nonvolatile memory (NVM) cell, comprising:
a select transistor on a first well of a semiconductor substrate, wherein the select transistor comprises a select gate, a first gate oxide layer between the select gate and the semiconductor substrate, a first sourcedrain doping region in the first well, and a second sourcedrain doping region spaced apart from the first sourcedrain doping region;
a floating gate transistor on the first well serially connected to the select transistor, wherein the PMOS floating gate transistor comprises a floating gate, a second gate oxide layer between the floating gate and the semiconductor substrate, the second sourcedrain doping region commonly shared by the select transistor, and a third sourcedrain doping region spaced apart from the second sourcedrain doping region;
a first salicide layer on the first sourcedrain doping region;
a protector oxide layer covering and being indirect contact with the floating gate;
a contact etch stop layer on the protector oxide layer such that the floating gate is isolated from the contact etch stop layer by the protector oxide layer;
a first sidewall spacer provided on either sidewall of the select gate; and
a second sidewall spacer provided on either sidewall of the floating gate, wherein the protector oxide layer covers and is in direct contact with a top surface of the floating gate, surfaces of the second sidewall spacers, entire surface of the second sourcedrain doping region, and only a portion of the third sourcedrain doping region.
2. The single-poly NVM cell according to claim 1 further comprising a UV blocking layer completely covering or being disposed directly above the floating gate.
3. The single-poly NVM cell according to claim 1 further comprising a deep N well disposed under the first well.
4. The single-poly NVM cell according to claim 1 wherein the first well is a medium-voltage N well.
5. The single-poly NVM cell according to claim 4 further comprising a high-voltage P well disposed under the medium-voltage N well, and an N type buried layer disposed under the high-voltage P well.
6. The single-poly NVM cell according to claim 1 wherein the floating gate may extend to capacitively couple to an erase gate region.
7. The single-poly NVM cell according to claim 6 wherein the protector oxide layer further completely covers the erase gate region.
8. The single-poly NVM cell according to claim 1 wherein the floating gate is further capacitively coupled to a control gate region and an erase gate region.
9. The single-poly NVM cell according to claim 8 wherein the protector oxide layer completely covers the control gate region and the erase gate region.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A system for receiving a signal, comprising:
a polarized antenna operative to receive a modulated signal;
a spectral estimator operatively connected to the polarized antenna and further operative to estimate the frequency spectrum of the modulated signal;
a spectral selector for extracting a set of frequencies from the estimated frequency spectrum of the modulated signal;
a clock detector operatively connected to the spectral selector and operative to detect a transmitter clock from the modulated signal; and
an demodulator for recovering the message signal.
2. The system of claim 1, wherein and the clock detector is further operative generate a phase-locked receiver clock from the transmitter clock.
3. The system of claim 1, wherein the polarized antenna is horizontally polarized.
4. The system of claim 1, wherein the polarized antenna is vertically polarized.
5. The system of claim 1, wherein the polarized antenna is horizontally polarized and further comprising a vertically polarized antenna operative to receive the modulated signal.
6. The system of claim 1, further comprising a data bit decider for receiving the message signal from the information decoder, the data bit decider operative to detect a data bit pattern within the modulated signal.
7. The system of claim 6, further comprising a synchronization element operative to synchronize the transmitter clock with a clock of the system.
8. The system of claim 2, further comprising a synchronization element operative to synchronize the phase-locked receiver clock with the transmitter clock.
9. The system of claim 1, further comprising a satellite housing.
10. The system of claim 1, wherein the demodulator comprises:
an information decoder operative to receive the modulated signal from the spectral estimator; and
data bit decision circuitry operatively connected to the information decoder
11. The system of claim 10, wherein the data bit decision circuitry comprises a Costas loop.
12. The system of claim 10, wherein the modulated signal is operative to transmit a data rate of at least 5 megabits per second through a frequency channel of about 50 kilohertz.
13. A satellite-based system for receiving a signal, comprising:
a polarized antenna operative to receive an ultra spectrally modulated signal;
a receiver filter centered at a receiver center frequency and having a receiver filter bandwidth, the receiver center frequency and the receiver filter bandwidth selected based on the transmitter center frequency and the transmitter filter bandwidth;
a clock detector for detecting a transmitter clock and generating a phase-locked receiver clock;
a demodulator for recovering the message signal; and
a satellite housing at least the receiver filter, clock detector, and demodulator.
14. The system of claim 13, wherein the polarized antenna is horizontally polarized.
15. The system of claim 13, wherein the polarized antenna is vertically polarized.
16. The system of claim 13, wherein the polarized antenna is horizontally polarized and further comprising a vertically polarized antenna operative to receive the modulated signal.
17. The system of claim 13, wherein the receiver center frequency comprises the transmitter center frequency.
18. The system of claim 13, wherein the receiver filter bandwidth comprises the transmitter filter bandwidth and a narrow band of frequencies added to the transmitter filter bandwidth.
19. The system of claim 13, wherein the demodulator comprises a correlator, a phase detector and data bit decision circuitry.
20. The system of claim 16, wherein the correlator comprises a matched filter.
21. The system of claim 16, wherein the data bit decision circuitry comprises a Costas loop.