1. A lid for closing a receptacle, said receptacle having a bottom and side walls that define a holding space, said lid comprising:
a generally polygonal cover plate adapted to cover a complementary shaped opening of said holding space in a closure position; and
mounting aids for mounting the lid on said receptacle, the mounting aids comprising:
a plurality of mounting aid elements extending from respective corners of said cover plate which, in the closure position, each overlap at least partly at least one of said receptacle side walls,
a plurality of positioning elements for guiding top edges of the receptacle side walls into a peripheral groove of the lid without becoming caught regardless of where the lid is initially placed on said top edges when commencing closure of the container, said groove being open in the direction of the holding space and defined by an inner groove side wall adapted to reside inside said holding space in said closure position and an outer groove side wall adapted to reside outside said holding space in said closure position,
a peripheral projection spaced inwardly from said inner groove sidewall to provide a channel between said inner groove side wall and said peripheral projection, said peripheral projection having a height less than that of said inner groove side wall, and
at least one web connecting a portion of said peripheral projection at one side of said lid to a portion of said peripheral projection at an opposite side of said lid,
each of said positioning elements spanning said channel and comprising a sloping surface starting from said peripheral projection and ending at a distal end of said inner groove side wall for providing said guiding.
2. A lid according to claim 1, wherein the lid has a lid rim which comprises a plurality of lid rim portions, in the closure position the lid rim at least partly overlaps a plurality of container walls and the lid rim bears the mounting aid elements.
3. A lid according to claim 1, wherein two non-parallel lid rim portions meet in a corner region of the lid and one lid corner or one corner region at most is disposed between two mounting aid elements.
4. A lid according to claim 1, wherein the lid corners of the cover plate are rounded and have a constant radius of curvature.
5. A lid according to claim 4, wherein the outer radius of curvature of the lid has a value of 4.5 cm at most in the region of the lid corner.
6. A lid according to claim 3, wherein at least two mounting aid elements are provided and the mounting aid elements are in each case disposed in a lid corner or a corner region.
7. A lid according to claim 6, wherein:
a first and a second lid edge, which meet in the lid corner, form a corner angle, each mounting aid element has a rim width over a corner angle region, and the corner angle region is greater than half the corner angle.
8. A lid according to claim 3, wherein a first lid rim portion has a maximum first lid rim portion width, a second lid rim portion, which meets the first lid rim portion in a corner region, has a maximum second lid rim portion width, the smaller width either of the maximum first or second lid rim portion width defines a minimum width, the first and the second lid rim portion form a corner angle, each mounting aid element has a rim width over a corner angle region, the corner angle region is greater than half the corner angle and the rim width of the corner angle region of the at least two mounting aid elements is greater than the minimum width or the difference of the two lid rim portion widths.
9. A lid according to claim 8, wherein the lid rim portion width of the second lid rim portions is approximately half as great as the lid rim portion width of the first lid rim portions.
10. A lid according to claim 7, wherein the corner angle is 90\xb0 or essentially 90\xb0 and the corner angle region is greater than 45\xb0.
11. A lid according to claim 10, wherein the corner angle region has at least a value of 75\xb0.
12. A lid according to claim 1, wherein the height of the inner groove side wall, starting from the cover plate, is smaller than the maximum height of the outer groove side wall.
13. A sterile container comprising:
a receptacle having a bottom and side walls that define a holding space for surgical instruments or material to be held in a sterile state, and
a generally polygonal lid for closing a complementary shaped opening of said receptacle, said lid comprising:
a cover plate adapted to cover said holding space in a closure position; and
mounting aids for mounting the lid on said receptacle, the mounting aids comprising:
a plurality of mounting aid elements extending from respective corners of said cover plate which, in the closure position, each overlap at least partly at least one of said receptacle side walls,
a plurality of positioning elements for guiding top edges of the receptacle side walls into a peripheral groove of the lid without becoming caught regardless of where the lid is initially placed on said top edges when commencing closure of the container, said groove being open in the direction of the holding space and defined by an inner groove side wall adapted to reside inside said holding space in said closure position and an outer groove side wall adapted to reside outside said holding space in said closure position,
a peripheral projection spaced inwardly from said inner groove sidewall to provide a channel between said inner groove side wall and said peripheral projection, said peripheral projection having a height less than that of said inner groove side wall, and
at least one web connecting a portion of said peripheral projection at one side of said lid to a portion of said peripheral projection at an opposite side of said lid,
each of said positioning elements spanning said channel and comprising a sloping surface starting from said peripheral projection and ending at a distal end of said inner groove side wall for providing said guiding.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A semiconductor circuit arrangement comprising:
a semiconductor substrate;
a first insulating layer, which is formed on the semiconductor substrate; and
an active semiconductor region, formed on the first insulating layer and laterally delimited by a second insulating layer;
wherein, in the active semiconductor region, a first and second doping zone of a first conduction type are formed as far as the surface of the first insulating layer for the definition of at least one channel zone, and there is formed at the surface of the at least one channel zone at least one gate dielectric and thereon a control electrode for the realization of a field effect transistor, wherein; and
wherein, in the active semiconductor region, at least one diode doping zone of a second conduction type, which is opposite to the first conduction type, is furthermore formed as far as the surface of the first insulating layer, which zone realizes at least one measuring diode via a diode side area with the first or second doping zone of the field effect transistor and is delimited by the second insulating layer at its further side areas.
2. The semiconductor circuit arrangement as claimed in claim 1, wherein the first or second doping zone of the field effect transistor directly adjoins the at least one diode doping zone for the realization of at least one PN diode.
3. The semiconductor circuit arrangement as claimed in claim 1, wherein the first or second doping zone of the field effect transistor is spaced apart from the at least one diode doping zone by an intrinsic semiconductor region for the realization of at least one PiN diode.
4. The semiconductor circuit arrangement as claimed in claim 1, wherein the field effect transistor constitutes a multi-gate field effect transistor having a multiplicity of fins in the region of the control electrode, wherein the fins are laterally delimited by the second insulating layer.
5. The semiconductor circuit arrangement as claimed in claim 1, wherein, at the surface of the doping zones, a blocking layer is formed in the region of the diode side area and a metal-semiconductor compound layer is formed in the remaining region not covered by the gate dielectric.
6. The semiconductor circuit arrangement as claimed in claim 1, wherein, at the surface of the doping zones, a dummy gate dielectric with an overlying dummy control electrode is formed in the region of the diode side area and a metal-semiconductor compound layer is formed in the remaining region not covered by the gate dielectric with the overlying control electrode.
7. The semiconductor circuit arrangement as claimed in claim 1, wherein the control electrode has a metallic material having a work function in the middle of the band gap of the semiconductor material of the active semiconductor region.
8. The semiconductor circuit arrangement as claimed in claim 1, wherein a width of the fins is significantly less than a gate length of the control electrode.
9. The semiconductor circuit arrangement as claimed in claim 1, wherein the second insulating layer constitutes an STI layer.
10. The semiconductor circuit arrangement as claimed in claim 1, wherein it constitutes a part of a temperature-compensated analog circuit.
11. A method for temperature detection in a semiconductor circuit, the method comprising:
providing a semiconductor substrate;
providing a first insulating layer on the semiconductor substrate;
providing an active semiconductor region on the first insulating layer that is laterally bounded by a second insulating layer;
providing a first and second doping zones of a first conduction type on the first insulating layer and in the active semiconductor region;
providing at least one channel zone bounded by the first and second doping zones;
providing at least one gate dielectric on the surface of the at least one channel zone;
providing a control electrode on the at least one gate dielectric;
providing at least one diode doping zone of a second conduction type, which is opposite to the first conduction type, on the surface of the first insulating layer and in the active semiconductor region;
impressing a diode measuring current in the forward direction on a measuring diode, and
measuring a diode voltage dropped across the measuring diode.
12. The method as claimed in claim 11, wherein the measured diode voltage is compared with a reference voltage.
13. The method as claimed in claim 11, wherein the temperature T to be measured is estimated from the equation:
UMD=0.5 V\u2212T\xd71.8 mVK
where UMD represents the measured diode voltage.
14. The method as claimed in claim, wherein the diode measuring current is less than 1100 of the drain current of the field effect transistor.
15. A semiconductor circuit comprising:
a semiconductor substrate;
a first insulating layer on the semiconductor substrate;
an active semiconductor region on the first insulating layer that is laterally bounded by a second insulating layer;
a first and second doping zones of a first conduction type on the first insulating layer and in the active semiconductor region;
at least one channel zone bounded by the first and second doping zones;
at least one gate dielectric on the surface of the at least one channel zone;
a control electrode on the at least one gate dielectric;
at least one diode doping zone of a second conduction type, which is opposite to the first conduction type, on the surface of the first insulating layer and in the active semiconductor region,
means for temperature detection via a voltage drop relative to the at least one diode doping zone.
16. The semiconductor circuit of claim 15, further comprising at least one measuring diode via a diode side area with the first or second doping zone that is bounded by the second insulating layer at its further side areas.
17. The semiconductor circuit of claim 15, wherein the first or second doping zone directly adjoins the at least one diode doping zone thereby forming at least one PN diode.
18. The semiconductor circuit of claim 15, wherein the first or second doping zone is spaced apart from the at least one diode doping zone by an intrinsic semiconductor region thereby forming at least one PiN diode.
19. The semiconductor circuit of claim 15, wherein the at least one channel zone bounded by the first and second doping zones forms a field effect transistor.
20. The semiconductor circuit of claim 19, wherein the field effect transistor constitutes a multi-gate field effect transistor having a multiplicity of fins in the region of the control electrode, wherein the fins are laterally delimited by the second insulating layer.