1. A method for decellularizing a tissue graft wherein said method comprises contacting a tissue graft with an extraction composition that comprises an amphoteric detergent at a concentration, and for a contact time, that is sufficient to rupture cells in the tissue, and wherein the method is performed in the absence of an anionic detergent.
2. The method, according to claim 1, wherein after decellularization the extracellular matrix structures remain intact and preservation is measurably equal to or better than when decellularized by methods that include an anionic detergent.
3. The method, according to claim 1, wherein no anionic detergent is applied to the tissue.
4. The method, according to claim 1, wherein Triton X-200\u2122 is not applied to the tissue.
5. The method, according to claim 1, wherein the tissue graft is contacted with sulfobetaine-10 (SB-10) andor sulfobetaine-16 (SB-16).
6. The method, according to claim 5, wherein the tissue graft is contacted with one extraction composition having a detergent component that consists of SB-10 and the tissue graft is also contacted with a second extraction composition having a detergent component that consists of SB-16.
7. The method, according to claim 1, wherein the concentration of the amphoteric detergent(s) is at least the critical micelle concentration.
8. The method, according to claim 1, wherein the extraction composition has physiologic, or greater, salinity.
9. The method, according to claim 1, further comprising at least one rinse step comprising contacting the tissue with a solution having less than physiologic salinity.
10. The method, according to claim 9, wherein the rinse solution has no salinity.
11. The method, according to claim 1, further comprising physically removing from the tissue non-structural debris.
12. The method, according to claim 1, further comprising freezing the tissue graft either before or after the decellularization process.
13. The method, according to claim 1, used to make a tissue graft selected from nerve, bone, intestinal, vascular, ligament, tendon, and heart grafts.
14. The method, according to claim 13, used to make a nerve graft.
15. The method, according to claim 14, wherein the tissue used to make the nerve graft is selected from nerve, muscle, placental, and vascular tissue.
16. The method, according to claim 1, further comprising introducing into the tissue graft one or more bioactive molecules or cells.
17. The method, according to claim 1, wherein the tissue graft’s neurite-promoting activity is retained after decellularization compared to nerves treated with buffer wash only.
18. The method, according to claim 1, wherein after decellularization the tissue graft’s neurite-promoting activity is retained and preservation is measurably equal to or better than when decellularized by methods that include an anionic detergent.
19. A tissue graft prepared by the method of claim 1.
20. A kit comprising a tissue graft of claim 19.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
Having thus described our invention, what we claim as new, and desire to secure by the Letters Patent is:
1. A process of fabricating a trench capacitor semiconductor memory structure comprising the steps of:
(a) providing a semiconductor structure comprising a semiconductor substrate or wafer having at least one storage trench region and a raised shallow trench isolation (STI) region adjacent to said storage trench, said structure having preformed layers of a partial gate conductor stack formed in said substrate or wafer which are spaced apart by said storage trench and raised STI regions;
(b) forming a bottom electrode layer in said storage trench region;
(c) forming a temperature sensitive high dielectric constant material on said bottom electrode layer and lining sidewalls of said storage trench region;
(d) forming a top electrode over said temperature sensitive high dielectric constant material;
(e) filling said storage trench region with polysilicon;
(f) completing fabrication of a capacitor in said storage trench region;
(g) forming a patterned gate conductor region from said preformed gate conductor stack layers; and
(h) forming subsequent device connections so as to complete fabrication of a trench capacitor semiconductor memory cell.
2. The process of claim 1 wherein said STI region and said partial GC stack layers are formed prior to fabrication of said trench storage capacitor.
3. The process of claim 1 wherein said semiconductor substrate or wafer is composed of a semiconducting material selected from the group consisting of Si, Ge, SiGe, GaAs, InAs, InP and all other IIIV compounds.
4. The process of claim 1 wherein said semiconductor substrate or wafer is composed of Si.
5. The process of claim 1 wherein said shallow trench isolation region includes a thermal silicon dioxide layer and a shallow trench isolation dielectric.
6. The process of claim 1 wherein said preformed partial gate conductor stack comprises a bottom gate oxide layer, a middle layer of polysilicon and a top barrier layer, wherein said layers are formed sequentially on the semiconductor substrate or wafer.
7. The process of claim 1 wherein said bottom and top electrodes are formed of the same or different conducting material selected from the group consisting of RuO2, SrRuO3, LaSrCoO, IrO2, Pt and Ir.
8. The process of claim 1 wherein said bottom and top electrodes are formed by a deposition process selected from the group consisting of chemical vapor deposition, metallo-organic chemical vapor deposition, electroplating and electrodeless plating.
9. The process of claim 1 wherein prior to step (b), a diffusion barrier layer is formed in said storage trench.
10. The process of claim 9 wherein said diffusion barrier layer is formed by chemical vapor deposition or physical vapor deposition.
11. The process of claim 9 wherein said diffusion barrier layer is composed of TiN, TiAlN, CoSi or TaSiN.
12. The process of claim 1 wherein said temperature sensitive high dielectric material is a material which may become unstable and also oxidize silicon when exposed to temperatures over 550 C. and has a dielectric constant of about 7 or higher.
13. The process of claim 12 wherein said temperature sensitive high dielectric constant material has a dielectric constant of from about 20 to about10,000.
14. The process of claim 1 wherein said temperature sensitive high dielectric constant material is a material selected from the group consisting of barium strontium titanium oxide (BSTO), lead zirconium titanium oxide (PZTO), strontium bismuth tantalate (SBT) and Ta2O5.
15. The process of claim 1 wherein said temperature sensitive high dielectric constant material is BSTO.
16. The process of claim 1 wherein said temperature sensitive high dielectric constant material is formed by a deposition process selected from the group consisting of chemical vapor deposition and sputtering.
17. The process of claim 1 wherein said polysilicon in step (e) is doped with a dopant.
18. The process of claim 17 wherein said dopant is a Ndopant.
19. The process of claim 1 wherein said storage trench region has a depth of from about 1 to about 10 m.
20. The process of claim 1 wherein after step (d), but prior to step (e), a conducting barrier is formed on said top electrode.
21. The process of claim 20 wherein said conducting barrier layer is TiN, TiAlN, CoSi or TiSiN.
22. The process of claim 17 further comprising subsequent gate sidewall oxidation and anneal steps which cause outdiffusion of the dopant from said polysilicon into said semiconductor substrate or wafer forming a buried-strap outdiffusion region whose lateral size is less than 50 nm.
23. The process of claim 22 wherein said lateral size of said outdiffusion region is between about 15 and about 30 nm.
24. A memory cell comprising
a capacitor formed in a trench located in a semiconductor substrate or wafer;
a MOSFET formed in said semiconductor substrate or wafer, said MOSFET comprising at least a patterned gate conductor stack and sourcedrain regions, said capacitor and said MOSFET being connected by a buried-strap outdiffusion region whose lateral outdiffusion is less than 50 nm.
25. The memory cell of claim 24 wherein said lateral outdiffusion is from about 15 to about 30 nm.
26. The memory cell of claim 24 wherein said buried-strap outdiffusion region is positioned adjacent to said capacitor.
27. The memory cell of claim 24 wherein said semiconductor substrate of wafer is composed of Si.
28. The memory cell of claim 24 wherein said capacitor comprises a temperature sensitive high dielectric constant material.
29. The memory cell of claim 28 wherein said temperature sensitive high dielectric material is a material which may become unstable and also oxidize silicon when exposed to temperatures over 550 C. and has a dielectric constant of about 7 or higher.
30. The memory cell of claim 29 wherein said temperature sensitive high dielectric constant material has a dielectric constant of from about 20 to about 10,000.
31. The memory cell of claim 28 wherein said temperature sensitive high dielectric constant material is a material selected from the group consisting of barium strontium titanium oxide (BSTO), lead zirconium titanium oxide (PZTO), strontium bismuth tantalate (SBT) and Ta2O5.
32. The memory cell of claim 28 wherein said temperature sensitive high dielectric constant material is BSTO.
33. A memory cell comprising
a capacitor formed in a trench located in a semiconductor substrate or wafer;
a MOSFET formed in said semiconductor substrate or wafer, said MOSFET comprising at least a patterned gate conductor stack, a near sourcedrain region located between said gate conductor stack and said capacitor, a far sourcedrain region located on a side of said gate conductor stack opposite said near sourcedrain region said capacitor and said MOSFET being connected by a buried-strap outdiffusion region laterally extending from an edge of said trench toward said gate conductor stack;
said capacitor and said sourcedrain regions having lateral dimensions photolithographically patterned to a minimum feature size of about 0.15 micron or smaller;
said memory cell characterized by a distance parameter, said parameter being the lateral distance between a near edge of said far sourcedrain region and a near edge of said outdiffusion region, said parameter having a value of between about 50% to greater than 75% of a lateral distance between said far gate conductor edge and said trench edge.