1. A memory unit comprising:
a flash memory having a main memory area and a spare memory area, wherein said main memory area includes a plurality of data storage registers and wherein each of said data storage registers has an address, and wherein said spare memory area has a storage capacity;
a display; and
a processor, wherein said processor transfers data stored in each of said addresses of said main memory area to said spare memory area upon a number of write operations performed to a respective one of said addresses in said main memory reaching a predetermined value, and wherein said processor drives said display to display an operational status representative of remaining write operations of said flash memory upon said number of write operations performed to a respective one of said addresses in said main memory reaching a predetermined number.
2. The memory unit as in claim 1, wherein said processor compares said number of write operation performed with a plurality of different values of said predetermined values, wherein the comparison produces a plurality of different results, and wherein said processor drives said display to display different operational statuses of said flash memory in different manners dependent upon said plurality of different results.
3. A memory unit comprising:
a flash memory having a main memory area and a spare memory area, wherein said main memory area includes a plurality of data storage registers and wherein each of said data storage registers has an address, and wherein said spare memory area has a storage capacity;
a display; and
a processor, wherein said processor transfers data stored in each of said addresses of said main memory area to said spare memory area upon an error frequency within one of said plurality of data storage registers reaching a predetermined frequency, and wherein said processor drives said display to display an operational status representative of error frequency of said flash memory upon said error frequency reaching a predetermined frequency.
4. The memory unit of claim 3, wherein said processor compares said error frequency with a plurality of different values of said predetermined values, wherein the comparison produces a plurality of different results, and wherein said processor drives said display to display different operational statuses of said flash memory in different manners dependent upon said plurality of different results.
5. A memory unit comprising:
a flash memory having a main memory area and a spare memory area, wherein said main memory area includes a plurality of data storage registers and wherein each of said data storage registers has an address, and wherein said spare memory area has a storage capacity;
a display; and
a processor wherein said processor transfers data stored in each of said addresses of said main memory area to said spare memory area upon a number of write operations performed to a respective one of said addresses in said main memory reaching a predetermined value, and wherein said processor drives said display to display a normal operational status representative of remaining write operations of said flash memory when the number of write operations has not reached a first set value, a warning operational status representative of remaining write operations of said flash memory when the number of write operations has reached the first set value but not a second set value, and an extreme limit operational status representative of remaining write operations of said flash memory when the number of write operations has reached a second set value.
6. The memory unit as in claim 5, wherein a remaining amount of the storage capacity in said spare memory does not reach a first set remaining amount in the normal operational status, and the remaining amount of the storage capacity reaches the first set remaining amount but does not exceed the second set remaining amount in the warning operational status, and the remaining amount of the storage capacity exceeds a second set remaining amount in the extreme limit operational status, and the display is driven to display the normal operational status, the warning operational status and the extreme limit operational status in a distinguishable manner.
7. The memory unit as in claim 6, wherein the normal operational status, the warning operational status and the extreme limit operational status are displayed in different manners.
8. The memory unit as in claim 7, wherein the normal operational status, the warning operational status and the extreme limit operational status are displayed by using different colors.
9. The memory unit as in claim 8, wherein the normal operational status, the warning operational status and the extreme limit operational status are displayed by using blue, yellow and red, respectively.
10. The memory unit as in claim 5, wherein the normal operational status, the warning operational status and the extreme limit operational status are displayed in different manners.
11. The memory unit as in claim 10, wherein the normal operational status, the warning operational status and the extreme limit operational status are displayed by using different colors.
12. The memory unit as in claim 11, wherein the normal operational status, the warning operational status and the extreme limit operational status are displayed by using blue, yellow and red, respectively.
13. A flash memory unit comprising:
a flash memory area, wherein said flash memory area stores data and wherein said flash memory area has a limited useful life in storing said data;
a spare memory area having a data storage capacity;
a display; and
a processor, wherein said processor transfers the stored data of said flash memory area to said spare memory area upon said flash memory approaching said limited useful life, and wherein said processor drives said display to display an operational status representative of remaining useful life of said flash memory by displaying an amount of remaining data storage capacity in said spare memory, wherein the operational status of the display provides an indication as to whether replacement of said flash memory area is required.
14. The flash memory unit of claim 13 wherein the limited useful life is indicated by an increase in error frequency or by a finite number of readwrite operations.
15. A flash memory unit utilizing error check code (ECC) comprising:
a flash memory having a main memory area and a spare memory area, wherein said main memory area includes a plurality of data storage addresses, and wherein said spare memory area includes a plurality of data storage addresses;
a display means; and
a processor, wherein said processor transfers data stored in each of said addresses of said main memory to one of said addresses of said spare memory area upon an error frequency of said one of said addresses in said main memory area reaching a predetermined value within the error frequency that a data error in said addresses of said main memory area can be corrected by said ECC stored in said flash memory, and
wherein said processor drives said display means to activate upon a remaining amount of storage capacity in said spare memory area reaching a predetermined value representative of error frequency and upon activation display an operational status of said flash memory.
16. The flash memory unit utilizing error check code (ECC) of claim 15, wherein said processor compares said error frequency with a plurality of different values of said predetermined values, and wherein said processor drives said display means to activate in different manners depending upon a plurality of comparison results and upon activation display different operational statuses of said flash memory.
17. The flash memory unit utilizing error check code (ECC) of claim 16, wherein a normal operational status, a warning operational status, and an extreme limit operational status of said flash memory are displayed in different manners.
18. A flash memory unit utilizing error check code (ECC) comprising:
a flash memory having a main memory area and a spare memory area, wherein said main memory area includes a plurality of data storage addresses, and wherein said spare memory area includes a plurality of data storage addresses;
a display means; and
a processor, wherein said processor transfers data stored in said main memory area to one of said addresses of said spare memory area upon the number of write operations performed to said addresses in said main memory area reaching a predetermined value representative of remaining write operations within possible number of write operations, and wherein said processor drives said display means to activate upon a remaining amount of storage capacity in said spare memory area reaching a predetermined value and upon activation display an operational status of said flash memory.
19. The flash memory unit utilizing error check code (ECC) of claim 18, wherein said processor compares said number of write operations to said addresses in said main memory area with a plurality of different values of said predetermined values, and wherein said processor drives said display means to activate in different manners depending upon a plurality of comparison results and upon activation display different operational statuses of said flash memory.
20. The flash memory utilizing Error Check Code (ECC) of claim 19, wherein a normal operational status, a warning operational status and an extreme limit operational status of said flash memory are displayed in different manners.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A method of generating an oscillating signal, comprising:
providing the oscillating signal as a first clock input to a first flip flop;
inverting the oscillating signal and providing the inverted oscillating signal as a second clock input to a second flip flop;
using the output of the first flip flop and the output of the second flip flop to generate a combined output that alternates between a logic low level and a logic high level; and using the combined output to sustain the oscillation of the oscillating signal.
2. A method as recited in claim 1, further comprising a clock buffer configured to buffer the oscillating signal.
3. A method as recited in claim 1, wherein the oscillating signal is provided to a primary circuit via a primary circuit buffer and further comprising an oscillating signal buffer configured to buffer the oscillating signal in the same manner that the primary circuit buffer buffers the oscillating signal as provided to the primary circuit.
4. A method as recited in claim 1, wherein the oscillating signal is sent to a field programmable gate array (FPGA).
5. A method as recited in claim 1, further comprising monitoring the oscillating signal.
6. A method as recited in claim 1, further comprising monitoring the oscillating signal and restarting the oscillator if it is determined that the output has ceased to oscillate.
7. The method of claim 1 further comprising providing a startup signal to generate a first pulse of the oscillating signal.
8. A method as recited in claim 1, wherein the oscillating signal is applied to a circuit that includes a circuit flip-flop, and the first and second flip-flops are substantially the same type as the circuit flip-flop.
9. A method as recited in claim 1, wherein the oscillating signal is applied to a circuit, and the oscillator resides on the same die as the circuit.
10. The method of claim 1 further comprising buffering the combined output and providing the buffered combined output as the oscillating signal.
11. An oscillator comprising:
a first element configured to toggle a first data output according to a first transition of an oscillating signal;
a second element configured to toggle a second data output according to a second transition of the oscillating signal;
a third element configured to receive the first data output and the second data output as inputs and provide the oscillating signal as output.
12. A method of generating an oscillating signal, comprising:
toggling a first data output according to a first transition of the oscillating signal;
toggling a second data output according to a second transition of the oscillating signal;
using the first data output and the second data output to generate an alternating output that sustains the oscillation of the oscillating signal.