1. An information processing device comprising a host device and a semiconductor memory device,
the host device comprising a main memory, and
the semiconductor memory device comprising
a nonvolatile semiconductor memory which stores first address conversion information and data,
a memory unit which stores second address conversion information, the second address conversion information being part of the first address conversion information, and
a controller which accesses the nonvolatile semiconductor memory by referring to the second address conversion information,
wherein third address conversion information is stored in the main memory, the third address conversion information being part of or all of the first address conversion information, and the controller uses the third address conversion information when accessing the nonvolatile semiconductor memory if address conversion information to be referred is not stored in the second address conversion information.
2. The device according to claim 1, wherein
the controller, when using the third address conversion information, refers to the address conversion information to be referred stored in the third address conversion information after transferred to the second address conversion information.
3. The device according to claim 1, wherein
the nonvolatile semiconductor memory further comprises a Dynamic Memory Access (DMA) controller, and
the DMA controller transfers address conversion information from the third address conversion information to the second address conversion information.
4. The device according to claim 1, wherein
the host device secures an area of the main memory, read part of or all of the first address conversion information stored in the nonvolatile semiconductor memory, and stores the read part of or all of the first address conversion information as the third address conversion information in the secured area of the main memory.
5. The device according to claim 1, wherein
the controller, when the address conversion information to be referred is not stored in the second address conversion information, executes an interrupt to the host device and acquires the address conversion information to be referred from the third address conversion information.
6. The device according to claim 1, wherein
the host device, when the address conversion information to be referred is not stored in the main memory, acquires the address conversion information to be referred from the first address conversion information.
7. A semiconductor memory device comprising:
a nonvolatile semiconductor memory which stores first address conversion information and data,
a memory unit which stores second address conversion information, the second address conversion information being part of the first address conversion information, and
a controller which accesses the nonvolatile semiconductor memory by referring to the second address conversion information,
wherein the controller refers to second address conversion information to be referred acquired from an external of the semiconductor memory device and accesses the nonvolatile semiconductor memory when accessing the nonvolatile semiconductor memory if address conversion information to be referred is not stored in the second address conversion information.
8. The device according to claim 7, further comprising a Dynamic Memory Access (DMA) controller,
wherein the DMA controller acquires the address conversion information to be referred from the external of the semiconductor memory device.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A semiconductor device comprising:
a gate stacked structure comprising a gate dielectric layer formed over a semiconductor substrate, a metal layer formed over the gate dielectric layer, and a capping layer formed over the metal layer,
wherein the capping layer includes a chemical element with a higher concentration at an interface between the capping layer and the metal layer than another region of the capping layer and the chemical element is operable to control an effective work function (eWF) of the gate stacked structure.
2. The semiconductor device of claim 1, wherein the chemical element comprises boron.
3. The semiconductor device of claim 1, wherein the capping layer comprises polysilicon or silicon germanium (SiGe).
4. The semiconductor device of claim 1, further comprising an interfacial layer formed between the gate dielectric layer and the semiconductor substrate,
wherein the gate dielectric layer has a larger dielectric constant than the interfacial layer.
5. The semiconductor device of claim 4, wherein the interfacial layer comprises silicon oxide and the gate dielectric layer has a larger dielectric constant than the silicon oxide.
6. The semiconductor device of claim 1, wherein the gate stacked structure becomes a gate stacked structure of an N-channel metal-oxide-semiconductor (NMOS).
7. A semiconductor device comprising an N-channel metal-oxide-semiconductor (NMOS) gate stacked structure and a P-channel metal-oxide-semiconductor (PMOS) gate stacked structure which are isolated from each other and formed over a semiconductor substrate,
wherein the NMOS gate stacked structure comprises a gate dielectric layer, a metal layer over the gate dielectric layer, a capping layer over the metal layer, the capping layer includes a chemical element having a higher concentration at an interface between the capping layer and the metal layer than another region of the capping layer, and the chemical element is operable to control an effective work function (eWF) of the NMOS gate stacked structure.
8. The semiconductor device of claim 7, wherein the chemical element comprises boron.
9. The semiconductor device of claim 7, wherein the capping layer comprise polysilicon or SiGe.
10. The semiconductor device of claim 7, further comprising an interfacial layer formed between the gate dielectric layer and the semiconductor substrate,
wherein the gate dielectric layer has a larger dielectric constant than the interfacial layer.
11. The semiconductor device of claim 10, wherein the interfacial layer comprises silicon oxide and the gate dielectric layer has a larger dielectric constant than the silicon oxide.
12. An N-channel metal-oxide-semiconductor (NMOS) comprising:
a semiconductor substrate having an N-channel;
a gate stacked structure comprising a gate dielectric layer formed over the N-channel, a metal layer formed over the gate dielectric layer, and a capping layer formed over the metal layer; and
a first capping layer including a higher concentration of boron at an interface between the metal layer and the capping layer than another region of the capping layer, wherein the boron is operable to control an effective work function (eWF) of the gate stacked structure.
13. The semiconductor device of claim 12, further comprising a second capping layer formed on the first capping layer, wherein the second capping layer does not include a higher concentration of the chemical element at an interface between the first and second capping layers than another region of the second capping layer.
14. The semiconductor device of claim 12, further comprising a metal layer formed over the first capping layer.
15. A method for fabricating a semiconductor device, comprising:
forming a gate dielectric layer over a semiconductor substrate;
forming a metal layer over the gate dielectric layer;
forming a capping layer over the metal layer, the capping layer including a chemical element for controlling an effective work function (eWF);
forming a gate stacked structure by etching the capping layer, the metal layer, and the gate dielectric layer; and
performing annealing to form a higher concentration of the chemical element at an interface between the capping layer and the metal layer than another region of the capping layer.
16. The method of claim 15, wherein the chemical element comprises boron.
17. The method of claim 15, wherein the annealing is performed by rapid thermal annealing (RTA).
18. The method of claim 15, wherein the forming of the capping layer comprises:
forming a first capping layer doped with the chemical element over the metal layer; and
forming a second capping layer over the first capping layer.
19. The method of claim 15, wherein the forming of the capping layer comprises forming a SiGe layer over the metal layer, the SiGe layer being in-situ doped with boron operable as the chemical element.
20. The method of claim 15, wherein the capping layer comprises polysilicon or SiGe.
21. The method of claim 15, further comprising forming an interfacial layer between the gate dielectric layer and the semiconductor substrate,
wherein the gate dielectric layer has a larger dielectric constant than the interfacial layer.
22. The method of claim 21, wherein the interfacial layer comprises silicon oxide and the gate dielectric layer has a larger dielectric constant than the silicon oxide.
23. A method for fabricating a semiconductor device, comprising:
forming a gate dielectric layer over a semiconductor substrate;
forming a metal layer over the gate dielectric layer;
forming a capping layer over the metal layer, wherein the capping layer includes a chemical element for controlling an effective work function (eWF);
forming a gate stacked structure by etching the capping layer, the metal layer, and the gate dielectric layer;
forming a sourcedrain by implanting impurities into the substrate; and
performing annealing to form a higher concentration of the chemical element at an interface between the capping layer and the metal layer than another region of the capping layer.
24. The method of claim 23, wherein the chemical element comprises boron.
25. The method of claim 23, wherein the annealing is performed by rapid thermal annealing (RTA).
26. The method of claim 23, wherein the forming of the capping layer comprises:
forming a first capping layer doped with the chemical element over the metal layer; and
forming a second capping layer over the first capping layer.
27. The method of claim 23, wherein the forming of the capping layer comprises forming a SiGe layer over the metal layer, the SiGe layer being in-situ doped with boron operable as the chemical element.
28. The method of claim 23, wherein the capping layer comprises polysilicon or SiGe.
29. The method of claim 23, further comprising forming an interfacial layer between the gate dielectric layer and the semiconductor substrate,
wherein the gate dielectric layer has a larger dielectric constant than the interfacial layer.
30. The method of claim 29, wherein the interfacial layer comprises silicon oxide and the gate dielectric layer has a larger dielectric constant than the silicon oxide.
31. The method of claim 23, wherein the chemical element comprises boron and the gate stacked structure becomes a gate stacked structure of an N-channel metal-oxide-semiconductor (NMOS).