1. An electrical connector comprising:
one or more dielectric and conductive elements having a plurality of electrical contacts arranged in a stair-step configuration on at least one surface; and
wherein in the stair-step configuration, the plurality of electrical contacts are disposed to mate with corresponding electrical contacts of one or more electrical components.
2. The electrical connector of claim 1, wherein the plurality of electrical contacts arranged in the stair-step configuration are disposed to mate with corresponding electrical contacts on a printed circuit board, and wherein the corresponding electrical contacts are arranged in a corresponding stair-step configuration.
3. The electrical connector of claim 1 wherein the plurality of electrical contacts form a plurality of stacked electrical contact assemblies;
a. wherein each assembly has a one or more conductive elements and a dielectric element;
b. wherein the one or more conductive elements of each assembly extend beyond the dielectric element of that assembly to expose a plurality of electrical contact points, the plurality of electrical contact points being provided on a common plane;
c. and wherein the plurality of electrical contact assemblies are disposed relative to each other to form a stepped structure, so that the electrical contact points of a given assembly in the plurality of assemblies extend a distance that is different than a the plurality of electrical contact points of an adjacent assembly in the plurality of assemblies.
4. The electrical connector in claim 3, wherein the one or more dielectric and conductive elements include ground planes.
5. The electrical connector in claim 3, wherein individual assemblies in the plurality of assemblies include dielectric material that aligns the plurality of electrical contacts of that assembly.
6. An electrical connector system comprising:
a. an electrical component having arrays of electrical contact pads arranged in a first stair-step configuration;
b. a connector interconnectable to the electrical component, the connector comprising one or more dielectric and conductive elements having a plurality of electrical contacts arranged in a second stair-step configuration on at least one surface.
7. An electrical connector for mating electrical components, wherein the electrical components are set at an angle to each other, and wherein the electrical connector comprises: a plurality of conductive elements wherein at least one of the conductive elements is comprised of a cantilever-beam, fixed at its mid-point, wherein the cantilever beam ends are arranged to protrude through openings in an insulating body assembly for creating electrical contact points.
8. The electrical connector in claim 7, further comprising a plurality of cantilever beam conductors, wherein the cantilever beam ends protrude through openings at different levels in a stair-step structure, creating electrical contact surfaces in a stair-step configuration.
9. The electrical connector in claim 7, wherein the ends of the cantilever beam conductor are bent to create an angle of approach for mating to electrical contact surfaces on electrical components.
10. The electrical connector of claim 7, wherein the electrical connector’s cantilever-beam signal conductors are mated on both sides with electrical components having stair-step electrical contact structures.
11. The electrical connector of claim 7, wherein at least one of the cantilever beam ends makes electrical contact with a conductive wire.
12. The electrical connector of claim 7, wherein at least one of the cantilever beam ends makes electrical contact with a signal trace in a flexible circuit.
13. An electrical interposer comprising:
a. a plurality of cantilever beam electrical conductors;
b. an insulating body assembly that captures the plurality of the cantilever-beam electrical conductors;
c. the plurality of cantilever-beam electrical conductors, bent and fixed at their mid-points and having contacts protruding through openings in the upper and lower surfaces of the insulating body assembly and having differing lengths, are disposed in an array whose arrays are on different surfaces of the insulating body assembly in a stair-step configuration.
14. An electrical connector comprising:
a. an insulating connector body containing channels with slots at the midpoints of either of the left and right side walls of the channels, the slots being perpendicular to the longitudinal axes of the channels;
b. a plurality of rigid, insulating beams with a pivot rod extending from both sides of the beam at its midpoint, the pivot rod inserted into the slots in the insulating body channels;
c. a plurality of conductive beams integral with and extending along the bottom of the plurality of rigid, insulating beams;
d. a plurality of leaf springs, each one above an aforementioned rigid, insulating beam, urging the plurality of conductive beams downward through openings at either end of the insulating body’s channels to create electrical contact points.
15. The electrical connector in claim 14 wherein the concave side of the leaf springs faces the rigid, insulating beams and its convex side faces upward.
16. The electrical connector in claim 14 wherein each leaf spring is replaced by two or more leaf springs laying one atop another in series configuration to reduce the leaf springs’ outer fiber mechanical stress and maintain electrical contact force.
17. The electrical connector in claim 14 wherein the leaf springs are replaced by other force mechanisms.
18. An electrical connector comprising:
a. a plurality of cantilever-beam signal conductors;
b. a plurality of push pins disposed and in electrical contact with the ends of the plurality of cantilever-beam signal conductors;
c. an insulating body with channels that fix or capture the centers of the plurality of cantilever-beam signal conductors and allow either end of the conductors to freely bend;
d. a location plates angularly disposed to each other, fixed to the sides of the insulating body, and containing, locating and guiding the push pins;
e. electrical components disposed at an angle to each other, whose electrical contact pads mate with and push on the push pins, which bend the cantilevered ends of the plurality of cantilever-beam signal conductors upward, which provide contact force between the ends of the push pins and the electrical components’ electrical contact pads, and provide contact force between the contact ends of the plurality of cantilever-beam signal conductors and the tops of the push pins thus providing electrical connection between the electrical components.
19. The electrical connector in claim 18 wherein the conductive collar on the push pin is changed into a dielectric or insulating material.
20. The electrical connector in claim 18 wherein projecting tabs are added to the sides of the push pin, said projecting tabs sliding up and down inside twisted slots in the location plates’ guiding holes thus twisting the push pin about its axis which provides contact wipe on the electrical contact pads of the mating electrical components and the ends of the cantilever-beam signal conductors.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A receiver circuit comprising:
a clock multiplier that multiplies a reference clock signal by an integer multiple to generate a multiplied reference clock signal;
an interpolator that adjusts a phase of the multiplied reference clock signal based upon a phase difference between a data clock signal and serial input data to generate the data clock signal;
a first divider circuit that generates, based at least in part upon the data clock signal, a timing reference signal having a frequency that is not an integer divisor of a frequency of the reference clock signal; and
a second divider circuit, in parallel with the first divider circuit, that generates a word clock signal by dividing the data clock signal by an integer value corresponding to a parallel data width of the serial input data.
2. The receiver circuit of claim 1, further comprising:
a sampler that samples the serial input data based upon the data clock signal.
3. The receiver circuit of claim 2, further comprising:
a deserializer that deserializes the sampled serial input data based upon the data clock signal and the word clock signal so as to generate parallel output data having the parallel data width.
4. A transmitter circuit comprising:
a clock multiplier that multiplies a reference clock signal by an integer multiple to generate a multiplied reference clock signal;
an interpolator that adjusts a phase of the multiplied reference clock signal based upon a phase difference between a first timing reference signal and a second timing reference signal to generate a data clock signal;
a first divider circuit that generates, based at least in part upon the data clock signal, the first timing reference signal having a frequency that is not an integer divisor of a frequency of the reference clock signal; and
a second divider circuit, in parallel with the first divider circuit, that generates a word clock signal by dividing the data clock signal by an integer value corresponding to a parallel data width of parallel input data.
5. The transmitter circuit of claim 4, further comprising:
a serializer that serializes the parallel input data based upon the data clock signal and the word clock signal so as to generate serial output data.
6. The transmitter circuit of claim 5, further comprising:
a driver that clocks the serial output data based upon the data clock signal.
7. A pleisiochronous repeater system comprising:
a receiver that receives serial input data, multiplies a receiver reference clock signal by a first integer multiple to generate a multiplied receiver reference clock signal, adjusts a phase of the multiplied receiver reference clock signal based upon a phase difference between a receiver data clock signal and serial input data to generate the receiver data clock signal, converts the serial input data into parallel output data, generates a receiver timing reference signal having a frequency that is not an integer divisor of a frequency of the receiver reference clock signal, based at least in part upon the receiver data clock signal, and generates a receiver word clock signal, in parallel with the receiver timing reference signal, by dividing the receiver data clock signal by an integer value corresponding to a parallel data width of the parallel output data; and
a transmitter that receives the parallel output data, multiplies a transmitter reference clock signal by a second integer multiple to generate a multiplied transmitter reference clock signal, adjusts a phase of the multiplied transmitter reference clock signal based upon a phase difference between the receiver timing reference signal and a transmitter timing reference signal to generate a transmitter data clock signal, converts the received parallel output data into serial output data, generates the transmitter timing reference signal having a frequency that is not an integer divisor of a frequency of the transmitter reference clock signal, based at least in part upon the transmitter data clock signal, and generates a transmitter word clock signal, in parallel with the transmitter timing reference signal, by dividing the transmitter data clock signal by an integer value corresponding to a parallel data width of the received parallel output data.
8. The system of claim 7, wherein the receiver timing reference signal and the transmitter timing reference signal are compared to generate a transmitter phase difference signal.
9. The system of claim 8, wherein the transmitter comprises:
a clock multiplier that multiplies the transmitter reference clock signal by the second integer multiple to generate the multiplied transmitter reference clock signal.
10. The system of claim 9, wherein the transmitter further comprises:
an interpolator that adjusts the phase of the multiplied transmitter reference clock signal based upon the transmitter phase difference signal.
11. The system of claim 7, wherein the transmitter further comprises:
a first divider circuit that generates the transmitter timing reference signal.
12. The system of claim 11, wherein the transmitter further comprises:
a second divider circuit that generates the transmitter word clock signal.
13. The system of claim 12, wherein the second divider circuit is resetable.
14. The system of claim 12, wherein the transmitter further comprises:
a serializer that serializes the received parallel output data based upon the transmitter data clock signal and the transmitter word clock signal so as to generate the serial output data.
15. The system of claim 14, wherein the transmitter further comprises:
a driver that clocks the serial output data based upon the transmitter data clock signal.
16. The system of claim 7, wherein the receiver comprises:
a clock multiplier that multiplies the receiver reference clock signal by the first integer multiple to generate the multiplied receiver reference clock signal.
17. The system of claim 16, wherein the receiver further comprises:
a sampler that samples the serial input data based upon the receiver data clock signal.
18. The system of claim 17, wherein the receiver further comprises:
an interpolator that adjusts the phase of the multiplied receiver reference clock signal based upon the phase difference between the receiver data clock signal and the serial input data to generate the receiver data clock signal.
19. The system of claim 17, wherein the receiver further comprises:
a first divider circuit that generates the receiver timing reference signal.
20. The system of claim 19, wherein the receiver further comprises:
a second divider circuit that generates the receiver word clock signal.
21. The system of claim 20, wherein the receiver further comprises:
a third divider circuit that generates a reset signal based upon the receiver word clock signal for resetting a fourth divider circuit in the transmitter.
22. The system of claim 20, wherein the receiver further comprises:
a deserializer that deserializes the sampled serial input data based upon the receiver data clock signal and the receiver word clock signal so as to generate the parallel output data having the parallel data width.
23. The system of claim 7, wherein the receiver is coupled directly to the transmitter.
24. The system of claim 7, wherein the receiver is coupled to the transmitter through at least one intermediate circuit.
25. The system of claim 24, wherein the at least one intermediate circuit comprises a FIFO that receives the parallel output data from the receiver and provides the parallel output data to the transmitter.
26. A method for operating a receiver circuit, the method comprising:
multiplying a reference clock signal by an integer multiple to generate a multiplied reference clock signal;
adjusting a phase of the multiplied reference clock signal based upon a phase difference between a data clock signal and serial input data to generate the data clock signal;
generating, based at least in part upon the data clock signal, a timing reference signal having a frequency that is not an integer divisor of a frequency of the reference clock signal; and
generating a word clock signal, in parallel with the timing reference signal, by dividing the data clock signal by an integer value corresponding to a parallel data width of serial input data.
27. At least one processor readable storage medium for storing a computer program of instructions configured to be readable by at least one processor for instructing the at least one processor to execute a computer process for performing the method as recited in claim 26.
28. A method for operating a transmitter circuit, the method comprising:
multiplying a reference clock signal by an integer multiple to generate a multiplied reference clock signal;
adjusting a phase of the multiplied reference clock signal based upon a phase difference between a first timing reference signal and a second timing reference signal to generate a data clock signal;
generating, based at least in part upon the data clock signal, the first timing reference signal having a frequency that is not an integer divisor of a frequency of the reference clock signal; and
generating a word clock signal, in parallel with the timing reference signal, by dividing the data clock signal by an integer value corresponding to a parallel data width of parallel input data.
29. At least one processor readable storage medium for storing a computer program of instructions configured to be readable by at least one processor for instructing the at least one processor to execute a computer process for performing the method as recited in claim 28.
30. A method of operation in a pleisiochronous repeater system, the method comprising:
receiving serial input data;
multiplying a receiver reference clock signal by a first integer multiple to generate a multiplied receiver reference clock signal;
adjusting a phase of the multiplied receiver reference clock signal based upon a phase difference between a receiver data clock signal and serial input data to generate the receiver data clock signal;
converting the serial input data into parallel output data;
generating, based at least in part upon the receiver data clock signal, a receiver timing reference signal having a frequency that is not an integer divisor of a frequency of the receiver reference clock signal;
generating a receiver word clock signal, in parallel with the receiver timing reference signal, by dividing the receiver data clock signal by an integer value corresponding to a parallel data width of the parallel output data;
receiving the parallel output data;
multiplying a transmitter reference clock signal by a second integer multiple to generate a multiplied transmitter reference clock signal;
adjusting a phase of the multiplied transmitter reference clock signal based upon a phase difference between the receiver timing reference signal and a transmitter timing reference signal to generate a transmitter data clock signal;
converting the received parallel output data into serial output data;
generating, based at least in part upon the transmitter data clock signal, the transmitter timing reference signal having a frequency that is not an integer divisor of a frequency of the transmitter reference clock signal; and
generating a transmitter word clock signal, in parallel with the transmitter timing reference signal, by dividing the transmitter data clock signal by an integer value corresponding to a parallel data width of the received parallel output data.
31. At least one processor readable storage medium for storing a computer program of instructions configured to be readable by at least one processor for instructing the at least one processor to execute a computer process for performing the method as recited in claim 30.