1. A chopper comparator having at least one logic gate in an input stage and a logic gate in an output stage, each logic gate in the input and output stages comprising:
an inverter circuit; and
a transistor for controlling connection and disconnection of the inverter circuit, wherein
an operation signal is supplied to the transistors to control operation of the logic gates in the input and output stages,
the inverter circuit becomes inactive when no operation of the chopper comparator is being performed, based on the operational signal,
one of the logic gates comprises a NAND gate including a pair of P channel MOS transistors is connected in parallel and a pair of N channel MOS transistors connected in series,
a first of the P channel MOS transistors and a first of the N channel MOS transistors of the NAND gate comprise the inverter circuit of the logic gate comprising a NAND gate, and
the operation signal is supplied to a second of the N channel MOS transistors to control the connection and disconnection of the inverter circuit.
2. The chopper comparator as claimed in claim 1, wherein
the operation signal is supplied to each gate of the second of the P and N channel MOS transistors in the NAND gate, and
a power source voltage is supplied through the second P channel MOS transistor to an output of the NAND gate.
3. A chopper comparator having at least one logic gate in an input stage and a logic gate in an output stage, each logic gate in the input and output stages comprising:
an inverter circuit; and
a transistor for controlling connection and disconnection of the inverter circuit, wherein
an operation signal is supplied to the transistors to control operation of the logic gates in the input and output stages,
the inverter circuit becomes inactive when no operation of the chopper comparator is being performed, based on the operation signal,
one of the logic gates comprises a NOR gate including a pair of P channel MOS transistors connected in series and a pair of N channel MOS transistors connected in parallel,
a first of the P channel MOS transistors and a first of the N channel MOS transistors of the NOR gate comprise the inverter circuit of the logic gate comprising a NOR gate, and
the operation signal is supplied to a second of the P channel MOS transistors to control the connection and disconnection of the inverter circuit.
4. The chopper comparator as claimed in claim 3, wherein
the operation signal is supplied to each gate of the second P and N channel MOS transistors in the NOR gate, and
the second of N channel MOS transistor connects an output section of the NOR gate to a ground when the P channel MOS transistor disconnects the inverter circuit, based on the operation signal.
5. A chopper comparator comprising at least one logic gate in an input stage including a switch closing and opening a short circuit of an input and an output of the input stage, and a logic gate in an output stage, the logic gates in each of the input and output stages comprising:
an inverter circuit; and
a transistor for controlling connection and disconnection of the inverter circuit, wherein
an operation signal is supplied to the transistor in the input stage, and a control signal is supplied to the transistor in the output stage,
the inverter circuit in the input stage becomes inactive, based on the control signal, during a non-operation period of the chopper comparator, and
when the switch is closed to short circuit the input and output of the input stage, the inverter circuit in the logic gate in the output stage becomes inactive, based on the control signal.
6. The chopper comparator as claimed in claim 5, wherein
the inverter of one of the logic gates comprises a P channel MOS transistor and a N channel MOS transistor connected in series, and
the transistor for controlling the connection and disconnection of the inverter is connected in series with one of the P and N channel MOS transistors of the inverter circuit.
7. The chopper comparator as claimed in claim 5, wherein
one of the logic gates comprises a NAND gate including a pair of P channel MOS transistors connected in parallel and a pair of N channel MOS transistors connected in series, and
a first of the P channel MOS transistors and a first of the N channel MOS transistors of the NAND gate comprise the inverter circuit of the logic gate comprising a NAND gate, wherein
the operation signal is supplied to a second of the N channel MOS transistors to control the connection and disconnection of the inverter circuit in the NAND gate in the input stage, and
the control signal is supplied to a second of the P channel MOS transistors to control the connection and disconnection of the inverter circuit in the NAND gate in the output stage.
8. The chopper comparator as claimed in claim 7, wherein
the operation signal is supplied to each gate of the second P and N channel MOS transistors in the NAND gates in the input stage,
a power source voltage is supplied to an output of the NAND gates in the input stage through the second P channel MOS transistor when the second N channel MOS transistor disconnects the inverter circuit in the NAND gate, based on the operation signal, and
the control signal is supplied to each gate of the second P and N channel MOS transistors in the NAND gate in the output stage, the power source voltage is supplied to an output of the NAND gate in the output stage through the second P channel MOS transistor when the second N channel MOS transistor disconnects the inverter circuit in the NAND gate in the output stage, based on the control signal.
9. The chopper comparator as claimed in claim 5, wherein
one of the logic gates comprises a NOR gate including a pair of P channel MOS transistors connected in series and a pair of N channel MOS transistors connected in parallel, and
a first of the P channel MOS transistors and a first of the N channel MOS transistors of the NOR gate comprise the inverter circuit of the logic gate comprising a NOR gate, wherein
the operation signal is supplied to the second of the P channel MOS transistors in the logic gate in the input stage to control connection and disconnection of the inverter circuit in the NOR gate in the input stage, and
the control signal is supplied to the second P and N channel MOS transistors in the NOR gate in the output stage to control the connection and disconnection of the inverter circuit in the NOR gate in the output stage.
10. The chopper comparator as claimed in claim 9, wherein
the inverter circuit in each NOR gate in the input and output stages is connected and disconnected by the second P channel MOS transistor of the NOR gates and the output of NOR gate is grounded by the second N channel MOS transistor of the NOR gate,
the operation signal is supplied to each gate of the second P and N channel MOS transistors in the NOR gates in the input stage, and the second N channel MOS transistor connects an output of the NOR gate in the input stage to a ground when second P channel MOS transistor disconnects the inverter circuit in the NOR gate in the input stage, based on the operation signal, and
the control signal is supplied to each gate of the second P and N channel MOS transistors in the NOR gates in the output stage, and the second N channel MOS transistor connects an output of the NOR gate in the output stage to the ground when the second P channel MOS transistor disconnects the inverter circuit in the NOR gate in the output stage, based on the control signal.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1-14. (canceled)
15. A computer readable storage medium comprising computer program code for an email or text message system providing the capability for a single email or text message to be individualized to each of one or more of a plurality of recipients or one or more subsets of the plurality of recipients.
16. The computer readable storage medium of claim 15, wherein the computer program code provides that upon the email or text message being sent, a portion of the email or text message that is individualized to a recipient or subset of recipients is not seen by the other of the plurality of recipients.
17. The computer readable storage medium of claim 15, wherein the email or text message system comprises a user interface.
18. The computer readable storage medium of claim 17, wherein the user interface is configured to allow individualized portions for each of multiple recipients or subsets of recipients.
19. The computer readable storage medium of claim 15, wherein the email or text message is a forwarded email or text message.
20. A method for providing email or text message text individualization, the method comprising:
providing a computer interface for individualizing at least a portion of an email or text message for a particular recipient or subset of recipients of a plurality of recipients.
21. The method of claim 20, further comprising:
sending the email or text message to the plurality of recipients;
wherein the individualized portion of the email or text message is not delivered or is made substantially invisible to the recipients that are not the particular recipient or part of the subset of recipients.
22. The method of claim 20, wherein the computer interface is configured to allow individualized portions for each of multiple recipients or subsets of recipients of the plurality of recipients.
23. The method of claim 21, wherein, for the particular recipient or subset of recipients, the individualized portion of the email or text message is appended to a general portion of the email or text message being sent to the plurality of recipients.
24. The method of claim 21, wherein the email or text message is a forwarded email or text message.
25. A method for private commenting on an email or text message, the method comprising:
providing a computer interface for adding a comment or remark to an email or text message that is associated with the email or text message but generally is not part of the email or text message.
26. The method of claim 25, wherein the comment or remark can be individually directed to one or more recipients of a plurality of recipients of the email or text message.
27. The method of claim 26, further comprising:
sending the email or text message and the associated comment or remark to the one or more recipients of the plurality of recipients; and
deleting the association of the comment or remark with the email or text message after the one or more recipients have first opened or viewed the email or text message and the one or more recipients have had a chance to read the comment or remark.
28. The method of claim 25, wherein the email or text message is a forwarded email or text message.
29. The method of claim 25, wherein the comment or remark is generally in the form of an instant message.
30. The method of claim 26, further comprising deleting the comment or remark after the email or text message is first opened or viewed by the one or more recipients and the one or more recipients have had a chance to read the comment or remark.
31. The method of claim 26, further comprising allowing the comment or remark to be saved by each of the one or more recipients.
32. The method of claim 27, further comprising allowing the comment or remark to be saved by each of the one or more recipients.
33. The method of claim 31, further comprising allowing each of the one or more recipients to associate the comment or remark with the email or text message.
34. The method of claim 26, further comprising blocking the one or more recipients from saving the comment or remark.