1. A method of removing SO2 from a flue gas stream comprising SO2 and SO3, the method comprising:
providing a source of trona;
injecting the trona into the flue gas stream, wherein the temperature of the flue gas is between about 600\xb0 F. and about 900\xb0 F.; and
maintaining the trona in contact with the flue gas for a time sufficient to react a portion of the trona with a portion of the SO2 and to react a portion of the trona with a portion of the SO3 to reduce the concentration of the SO2 and the SO3 in the flue gas stream.
2. The method of claim 1 wherein the mean particle size of the trona is less than about 40 micron.
3. The method of claim 1 wherein the mean particle size of the trona is between about 10 micron and about 40 micron.
4. The method of claim 1 wherein the mean particle size of the trona is between about 24 micron and about 28 micron.
5. The method of claim 1 wherein the temperature of the flue gas is greater than about 630\xb0 F.
6. The method of claim 1 wherein the temperature of the flue gas is greater than about 700\xb0 F.
7. The method of claim 1 wherein the temperature of the flue gas is less than about 800\xb0 F.
8. The method of claim 1 wherein the temperature of the flue gas is less than about 750\xb0 F.
9. The method of claim 1 wherein the temperature of the flue gas is between about 700\xb0 F. and about 750\xb0 F.
10. The method of claim 1 wherein the trona is injected at a rate with respect to the flow rate of the SO2 to provide a normalized stoichiometric ratio of sodium to sulfur of between about 1.0 and 1.5.
11. The method of claim 1 wherein the trona is injected as a dry material.
12. The method of claim 1 further comprising milling the trona to a desired mean particle size at a location proximate the flue gas stream.
13. The method of claim 1 further comprising collecting a reaction product of the trona and the SO2 in an electrostatic precipitator.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A data bus synchronizer comprising:
a plurality of registers arranged in a cascade, configured to generate a synchronized output in response to sampling an asynchronous bus without an enable signal, wherein the plurality of registers receive a value on the asynchronous bus and wherein the asynchronous bus is synchronized to a control clock input such that a latest stable value on the asynchronous bus is always sampled, irrespective of a toggling rate of the asynchronous bus with respect to the control clock input, thereby generating the synchronized output;
a last register of the plurality of registers, configured to generate the synchronized output in response to a load enable signal; and
a logic block that is configured to generate the load enable signal on satisfaction of a logic condition.
2. The data bus synchronizer of claim 1, wherein the value received at the plurality of registers is a multi bit signal.
3. The data bus synchronizer of claim 1, wherein the logic condition is ((REG3==REG2) AND (REG3==SYNC_OUT)), wherein:
REG2 and REG3 are two subsequent registers prior to the last register;
SYNC_OUT is the synchronized output generated by the data bus synchronizer;
(REG3==REG2) indicates that a stable value on the asynchronous bus has been sampled;
(REG3==SYNC_OUT) checks if the latest stable value is different from the synchronized output; and
SYNC_OUT is generated when both (REG3==REG2) and (REG3==SYNC_OUT).
4. The data bus synchronizer of claim 1, wherein any value on the asynchronous bus is sampled when the asynchronous bus toggles at one third the toggling rate of the control clock input.
5. The data bus synchronizer of claim 1, wherein a maximum tolerable skew rate is generated by subtracting from a clock period of the control clock input, a setup hold time for an edge of the control clock input.
6. A phase locked loop comprising:
a phase locked loop controller configured to generate a clock divider value on an asynchronous bus;
a divider controller receiving the clock divider value and a control clock input, configured to generate a division value, wherein the divider controller comprises a data bus synchronizer; wherein the data bus synchronizer further comprises:
a plurality of registers arranged in a cascade, configured to generate a synchronized output in response to sampling an asynchronous bus without an enable signal, wherein the plurality of registers receive a value on the asynchronous bus and wherein the asynchronous bus is synchronized to a control clock input such that a latest stable value on the asynchronous bus is always sampled, irrespective of a toppling rate of the asynchronous bus with respect to the control clock input, thereby generating the synchronized output; a last register of the plurality of registers, configured to generate the synchronized output in response to a load enable signal; and
a logic block that is configured to generate the load enable signal on satisfaction of a logic condition; and
a divider configured to generate a clock output in response to the division value and a phase locked loop clock input.
7. The phase locked loop of claim 6, wherein the value received at the plurality of registers is a multi bit signal.
8. The phase locked loop of claim 6, wherein the logic condition being ((REG3==REG2) AND (REG3==SYNC_OUT)); wherein:
REG2 and REG3 are two subsequent registers prior to the last register;
SYNC_OUT is the synchronized output generated by the data bus synchronizer;
(REG3==REG2) indicates that a stable value on the asynchronous bus has been sampled;
(REG3==SYNC_OUT) checks if the latest stable value is different from the synchronized output; and
SYNC_OUT is generated when both (REG3==REG2) and (REG3==SYNC_OUT).
9. The phase locked loop of claim 6, wherein any value on the asynchronous bus is sampled when the asynchronous bus toggles at one third the toggling rate of the control clock input.
10. The phase locked loop of claim 6, wherein a maximum tolerable skew rate is generated by subtracting from a clock period of the control clock input, a setup hold time for an edge of the control clock input.
11. A method of generating a synchronized output from an asynchronous bus input, comprising:
applying a value on an asynchronous bus to a plurality of registers arranged in a cascade;
sampling the asynchronous bus directly without an enable signal wherein sampling includes sampling a latest stable value on the asynchronous bus irrespective of a toggling rate of the asynchronous bus with respect to a control clock input; and sampling every value on the asynchronous bus when the toggling rate of the asynchronous bus is one third the toggling rate of the control clock input;
generating a load enable signal on satisfaction of a logic condition; and
configuring a last register of the plurality of registers to generate the synchronized output in response to the load enable signal.
12. The method of claim 11, wherein generating comprises:
comparing if data in two registers preceding the last register are same;
comparing if data of a register preceding the last register and the synchronized output are different; and
generating the load enable signal only if data in two registers preceding the last register are same and data of the register preceding the last register and the synchronized output are different.
13. The method of claim 11, further comprising:
synchronizing the asynchronous bus to the control clock input such that the latest stable value on the asynchronous bus is always sampled, thereby generating the synchronized output.
14. The method of claim 11, further comprising:
subtracting from a clock period of the control clock input, a setup hold time for an edge of the control clock input, to generate a maximum tolerable skew rate.