1. An electronic locking mechanism for a vehicle differential assembly, the electronic locking mechanism comprising:
a lock element movable in response to an actuation signal between an open position and a locked position, said lock element configured to permit a first side gear and a second side gear to turn at varying rates relative to one another when said lock element is in said open position, said lock element further configured to force the side gears to turn generally at a same rate when said lock element is in said locked position; and
a processor configured to determine a status of the differential assembly from a current profile, said current profile including the actuation signal and an induced current;
wherein said determined differential assembly status includes one of an activated and locked status, an activated but unlocked status, a deactivated but locked status, and a deactivated and unlocked status.
2. The electronic locking mechanism of claim 1, said processor further configured such that said activated and locked status is determined when said lock element is in said locked position and the differential assembly is locked;
said activated but unlocked position is determined when said lock element is actuated to be in said locked position and the differential assembly is unlocked;
said deactivated but locked position is determined when said lock element is actuated to be in said unlocked position and the differential assembly is locked; and
said deactivated and unlocked position is determined when said lock element is actuated to be in said unlocked position and the differential assembly is unlocked.
3. The electronic locking mechanism of claim 1, further comprising:
a solenoid in communication with the actuation signal; and
a plunger element actuated by the solenoid;
wherein said plunger element generates said induced current.
4. The electronic locking mechanism of claim 1, wherein said induced current is generated by movement of said lock element.
5. The electronic locking mechanism of claim 1, wherein said processor is further configured to monitor said current profile for a first deviation, determine a first deviation depth of said first deviation, and assign said differential assembly status based on said first deviation depth.
6. The electronic locking mechanism of claim 1, wherein said processor is further configured to continue to monitor said current profile for a second deviation if said first deviation depth indicates an activated but unlocked status, wherein said activated but unlocked status is associated with said lock element being positioned between said open position and said locked position.
7. The electronic locking mechanism of claim 1, wherein said processor is further configured to monitor said current profile for a quick first spike, said quick first spike occurring in a primary transition of said current profile associated with said lock element moving out of said locked position, monitor said current profile for a delayed first spike if said quick first spike is absent, and determine said differential assembly status based on the presence of one of said quick spike and said delayed first spike.
8. A differential assembly for a vehicle comprising:
a first side gear secured to a first side shaft for rotation therewith;
a second side gear secured to a second side shaft for rotation therewith;
a differential case generally housing said first side gear and said second side gear;
an electronic locking mechanism movable between an open position and a locked position in response to an actuation signal from a power wire, said locking mechanism configured to permit said side gears to turn at varying rates relative to one another when said locking mechanism is in said open position, said locking mechanism further configured to force the side gears to turn at a generally same rate when said locking mechanism is in said locked position; and
a processor configured to determine a status of the differential assembly from a current profile, said current profile including the actuation signal and an induced current;
wherein said determined differential assembly status includes one of an activated and locked status, an activated but unlocked status, a deactivated but locked status, and a deactivated and unlocked status.
9. The differential assembly of claim 8, said processor further configured such that said activated and locked status is determined when said locking mechanism is in said locked position and the differential assembly is locked;
said activated but unlocked position is determined when said electronic locking mechanism is actuated to be in said locked position and the differential assembly is unlocked;
said deactivated but locked position is determined when said electronic locking mechanism is actuated to be in said unlocked position and the differential assembly is locked; and
said deactivated and unlocked position is determined when said electronic locking mechanism is in said unlocked position and the differential assembly is unlocked.
10. The differential assembly of claim 8, further comprising:
a solenoid in communication with the actuation signal; and
a plunger element actuated by the solenoid;
wherein said plunger element generates said induced current.
11. The differential assembly of claim 9, further comprising a cam ring in communication with said plunger element, said solenoid element selectively moving said cam ring with said plunger element into said locked position wherein a cam face gear on said cam ring engages a lock face gear on said second side gear.
12. The differential assembly of claim 11, further comprising a pressure plate mounted to said cam ring, wherein said processor is configured to generally monitor movement of said pressure plate.
13. The differential assembly of claim 8, wherein said current profile is generated by superpositioning said induced current onto said actuation signal in the power wire, said induced current associated with movement of said electronic locking mechanism.
14. The differential assembly of claim 8, wherein said processor is further configured to monitor said current profile for a first deviation, determine a first deviation depth of said first deviation, and assign said differential assembly status based on said first deviation depth, continue to monitor said current profile for a second deviation if said first deviation depth indicates an activated but unlocked status, wherein said activated but unlocked status is associated with said electronic locking mechanism being positioned between said open position and said locked position.
15. The differential assembly of claim 8, wherein said processor is further adapted to monitor said current profile for a quick first spike, said quick first spike occurring in a primary downslope of said current profile associated with said electronic locking mechanism moving out of said locked position, monitor said current profile for a delayed first spike if said quick first spike is absent, and determine said differential assembly status based on the presence of one of said quick spike and said delayed first spike.
16. A method, comprising:
receiving an activation signal through a power wire at an electronic locking mechanism of a differential assembly, the differential assembly including two side shafts, each of the side shafts having associated side gears, the differential assembly further including a differential case generally housing the first and second side gears, said electronic locking mechanism moving in response to said activation signal between an open position, wherein the side gears are permitted to turn at varying rates with respect to each other, and a locked position, wherein the side gears are forced to turn at a same rate, said electronic locking mechanism configured to selectively lock and unlock the differential assembly;
monitoring a current profile in said power wire; and
determining a status of said differential from said current profile, said status including one of an activated and locked position, an activated but unlocked position, a deactivated but locked position, and a deactivated and unlocked position.
17. The method of claim 16, further comprising:
determining said activated and locked status when said electronic locking mechanism is in said locked position and the differential assembly is locked;
determining said activated but unlocked status when said electronic locking mechanism is in said locked position and the differential assembly is unlocked;
determining said deactivated but locked status when said electronic locking mechanism is in said unlocked position and the differential assembly is locked; and
determining said deactivated and unlocked status when said electronic locking mechanism is in said unlocked position and the differential assembly is unlocked.
18. The method of claim 16, further comprising:
monitoring said current profile for a first deviation;
determining a first deviation depth of said first deviation; and
determining said status of the differential assembly based at least upon said first deviation depth.
19. The method of claim 18, further comprising:
determining an activated but unlocked status of said differential assembly from said first deviation depth;
continuing to monitor said current profile for a second deviation; and
determining said differential assembly status based upon at least said second deviation.
20. The method of claim 19, further comprising:
determining a second deviation depth of said second deviation; and
determining said differential assembly status based on said second deviation depth.
21. The method of claim 16, further comprising:
monitoring said current profile for a quick first spike, said quick first spike occurring during a primary transition of said current profile;
monitoring said current profile for a delayed first spike if said quick first spike is absent; and
determining said differential assembly status based on the presence of one of said quick first spike and said delayed first spike.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. An integrated circuit, comprising:
a plurality of first memory cells arranged along a first line;
a first contact coupled to the plurality of first memory cells;
a plurality of second memory cells arranged along a second line;
a second contact coupled to the plurality of second memory cells; and
a plurality of switching elements, wherein two adjacent switching elements are coupled with each other, wherein a first switching element of the two adjacent switching elements is coupled to the first contact and a second switching element of the two adjacent switching elements is coupled to the second contact and wherein the two adjacent switching elements are of the same type of switching element.
2. The integrated circuit of claim 1, wherein the first memory cells and the second memory cells comprise non-volatile memory cells.
3. The integrated circuit of claim 1,
wherein the plurality of first memory cells comprise serially source-to-drain coupled memory cells that form a first memory cell string;
wherein the first contact is coupled to a portion of the serial coupling of the first memory cell string;
wherein the plurality of second memory cells comprise serially source-to-drain coupled memory cells that form a second memory cell string; and
wherein the second contact is coupled to a portion of the serial coupling of the second memory cell string.
4. The integrated circuit of claim 1, wherein the type of switching element is determined by a switching characteristic of the switching element.
5. The integrated circuit of claim 4, wherein the type of switching element is determined by a control characteristic of the switching element.
6. The integrated circuit of claim 1, wherein the plurality of switching elements comprise transistors.
7. The integrated circuit of claim 6, wherein the plurality of switching elements comprise field effect transistors.
8. The integrated circuit of claim 1, wherein at least one switching element of the plurality of switching elements comprises a normally-on switching element.
9. The integrated circuit of claim 1, wherein at least one switching element of the plurality of switching elements comprises a normally-off switching element.
10. The integrated circuit of claim 1, further comprising:
a first select line to select the plurality of first memory cells, the first select line crossing the first line and the second line, wherein the first select line is coupled to the first switching element and to the second switching element; and
a second select line to select the plurality of second memory cells, the second select line crossing the first line and the second line;
wherein the plurality of switching elements further comprise a third switching element that is serially coupled to the first switching element, and a fourth switching element, that is serially coupled to the second switching element, and
wherein the second select line is coupled to the third switching element and to the fourth switching element.
11. The integrated circuit of claim 10,
wherein the first switching element and the third switching element are different types of switching elements; and
wherein the second switching element and the fourth switching element are different types of switching elements.
12. The integrated circuit of claim 10, wherein the third switching element and the fourth switching element are the same type of switching element.
13. The integrated circuit of claim 10,
wherein the first switching element and the second switching element comprise normally-on switching elements; and
wherein the third switching element and the fourth switching element comprise normally-off switching elements.
14. The integrated circuit of claim 1, further comprising a plurality of control lines to control the first memory cells and the second memory cells.
15. The integrated circuit of claim 14, wherein the plurality of control lines cross the first line and the second line.
16. The integrated circuit of claim 15, wherein the first select line and the second select line are arranged between the plurality of control lines and the first contact and the second contact.
17. The integrated circuit of claim 16, wherein the first select line and the second select line are arranged substantially in parallel to the plurality of control lines.
18. The integrated circuit of claim 1,
wherein the first line and the second line have a line pitch of a predefined feature size; and
wherein the first contact and the second contact have a contact pitch of at least twice the predefined feature size.
19. The integrated circuit of claim 1, wherein the first memory cells and the second memory cells comprise charge storing memory cells.
20. The integrated circuit of claim 19, wherein the first memory cells and the second memory cells comprise floating gate memory cells or charge trapping memory cells.
21. The integrated circuit of claim 1, wherein the first contact and the second contact are arranged relative to one another such that they have substantially no overlap in a direction that is substantially perpendicular to the first line or the second line.
22. An integrated circuit of claim 1, further comprising:
a plurality of third memory cells arranged along a third line;
a third contact coupled to the plurality of third memory cells;
a plurality of fourth memory cells arranged along a fourth line;
a fourth contact coupled to the plurality of fourth memory cells;
a second group of a plurality of switching elements, wherein two adjacent switching elements are coupled with each other, wherein a third switching element of the two adjacent switching elements is coupled to the third contact and a fourth switching element of the two adjacent switching elements is coupled to the fourth contact, wherein the third switching element and the fourth switching element are of a second type of switching element, which is different from the first type of switching element;
a plurality of fifth memory cells arranged along a fifth line;
a fifth contact coupled to the plurality of fifth memory cells;
a plurality of sixth memory cells arranged along a sixth line;
a sixth contact coupled to the plurality of sixth memory cells; and
a third group of a plurality of switching elements, wherein two adjacent switching elements are coupled with each other, wherein a fifth switching element of the two adjacent switching elements is coupled to the fifth contact and a sixth switching element of the two adjacent switching elements is coupled to the sixth contact, wherein the fifth switching element and the sixth switching element are of the first type of switching element.
23. An integrated circuit having a switching field, the switching field comprising:
a first group of a plurality of switching elements, wherein two adjacent switching elements are coupled with each other, wherein a first switching element of the two adjacent switching elements is coupled to a first contact of first memory cells and a second switching element of the two adjacent switching elements is coupled to a second contact of second memory cells, wherein the first switching element and the second switching element are of a first type of switching element;
a third group of a plurality of switching elements next to the first group of a plurality of switching elements, wherein two adjacent switching elements are coupled with each other, wherein a fifth switching element of the two adjacent switching elements is coupled to a fifth contact of fifth memory cells and a sixth switching element of the two adjacent switching elements is coupled to a sixth contact of sixth memory cells, wherein the fifth switching element and the sixth switching element are of the first type of switching element; and
a second group of a plurality of switching elements arranged between the first group of a plurality of switching elements and the third group of a plurality of switching elements, wherein two adjacent switching elements are coupled with each other, wherein a third switching element of the two adjacent switching elements is coupled to a third contact of third memory cells and a fourth switching element of the two adjacent switching elements is coupled to a fourth contact of fourth memory cells, wherein the third switching element and the fourth switching element are of a second type of switching element, which is different from the first type of switching element.
24. A method for manufacturing an integrated circuit, the method comprising:
forming a plurality of first memory cells along a first line;
forming a first contact coupled to the plurality of first memory cells;
forming a plurality of second memory cells along a second line;
forming a second contact coupled to the plurality of second memory cells; and
forming a plurality of switching elements, wherein two adjacent switching elements are coupled with each other, wherein a first switching element of the two adjacent switching elements is coupled to the first contact and a second switching element of the two adjacent switching elements is coupled to the second contact and wherein the two adjacent switching elements are of the same type of switching element.
25. The method of claim 24, wherein the first memory cells and the second memory cells are formed as non-volatile memory cells.
26. The method of claim 24,
wherein the plurality of first memory cells are serially source-to-drain coupled, thereby forming a first memory cell string;
wherein the first contact contacts a portion of the serial coupling of the first memory cell string;
wherein the plurality of second memory cells are serially source-to-drain coupled, thereby forming a second memory cell string; and
wherein the second contact contacts a portion of the serial coupling of the second memory cell string.
27. The method of claim 24, wherein at least one switching element of the plurality of switching elements is formed as a normally-off switching element.
28. The method of claim 24, further comprising forming a plurality of control lines to control the first memory cells and the second memory cells.
29. The method of claim 28, wherein the control lines and the switching elements are formed using the same manufacturing process.
30. The method of claim 28, wherein the control lines and the switching elements are formed simultaneously.
31. A method for manufacturing an integrated circuit, the method comprising:
forming a first group of a plurality of switching elements, wherein two adjacent switching elements are coupled with each other, wherein a first switching element of the two adjacent switching elements is coupled to a first contact of first memory cells and a second switching element of the two adjacent switching elements is coupled to a second contact of second memory cells, wherein the first switching element and the second switching element are of a first type of switching element;
forming a third group of a plurality of switching elements next to the first group of a plurality of switching elements, wherein two adjacent switching elements are coupled with each other, wherein a fifth switching element of the two adjacent switching elements is coupled to a fifth contact of fifth memory cells and a sixth switching element of the two adjacent switching elements is coupled to a sixth contact of sixth memory cells, wherein the fifth switching element and the sixth switching element are of the first type of switching element; and
forming a second group of a plurality of switching elements arranged between the first group of a plurality of switching elements and the third group of a plurality of switching elements, wherein two adjacent switching elements are coupled with each other, wherein a third switching element of the two adjacent switching elements is coupled to a third contact of third memory cells and a fourth switching element of the two adjacent switching elements is coupled to a fourth contact of fourth memory cells, wherein the third switching element and the fourth switching element are of a second type of switching element, which is different from the first type of switching element.
32. A memory module, comprising:
a plurality of integrated circuits arranged as a module, wherein at least one integrated circuit of the multiplicity of integrated circuits comprises:
a plurality of first memory cells arranged along a first line;
a first contact coupled to a portion of the first line;
a plurality of second memory cells arranged along a second line;
a second contact coupled to a portion of the second line; and
a plurality of switching elements, wherein two adjacent switching elements are coupled with each other, wherein a first switching element of the two adjacent switching elements is coupled to the first contact and a second switching element of the two adjacent switching elements is coupled to the second contact and wherein the two adjacent switching elements are of the same type of switching element.
33. The memory module of claim 32, wherein the memory module is a stackable memory module in which at least some of the integrated circuits are stacked one above the other.
34. A computing system, comprising:
a processing apparatus;
an input apparatus coupled to the processing apparatus;
an output apparatus coupled to the processing apparatus; and
a memory cell arrangement coupled to the processing apparatus, the memory cell arrangement comprising:
a plurality of first memory cells arranged along a first line;
a first contact coupled to the plurality of first memory cells;
a plurality of second memory cells arranged along a second line;
a second contact coupled to the plurality of second memory cells; and
a plurality of switching elements, wherein two adjacent switching elements are coupled with each other, wherein a first switching element of the two adjacent switching elements is coupled to the first contact and a second switching element of the two adjacent switching elements is coupled to the second contact and wherein the two adjacent switching elements are of the same type of switching element.
35. An integrated circuit, comprising:
a plurality of first memory cells arranged along a first line;
a plurality of second memory cells arranged along a second line;
a plurality of switching elements, wherein a first switching element is coupled to the first memory cells and a second switching element is coupled to the second memory cells;
a first select line to select the plurality of first memory cells crossing the first line and the second line; and
a second select line to select the plurality of second memory cells crossing the first line and the second line;
wherein the first switching element comprises a control gate region that comprises a portion overlapping the first select line and a portion overlapping the second select line.
36. The integrated circuit of claim 35, wherein the control gate region extends along the first line.
37. The integrated circuit of claim 35, wherein the second switching element comprises a control gate region that comprises a portion overlapping the first select line and a portion overlapping the second select line,
38. The integrated circuit of claim 37, wherein the control gate region extends along the second line.
39. The integrated circuit of claim 35, wherein the first memory cells and the second memory cells comprise non-volatile memory cells.
40. The integrated circuit of claim 35,
wherein the plurality of first memory cells are serially source-to-drain coupled, thereby forming a first memory cell string; and
wherein the plurality of second memory cells are serially source-to-drain coupled, thereby forming a second memory cell string.
41. The integrated circuit of claim 35, wherein the plurality of switching elements comprise a transistor.
42. The integrated circuit of claim 41, wherein the plurality of switching elements comprise a field effect transistor.
43. The integrated circuit of claim 42, wherein the first switching element or the second switching element has a floating gate structure comprising:
a tunnel dielectric;
a floating gate disposed above the tunnel dielectric as the control gate region;
a control gate dielectric disposed above the floating gate; and
a control gate disposed above the control gate dielectric.
44. The integrated circuit of claim 35, further comprising a plurality of control lines to control the first memory cells and the second memory cells.
45. The integrated circuit of claim 44, wherein the plurality of control lines are crossing the first line and the second line.
46. The integrated circuit of claim 44, wherein the first select line and the second select line are arranged between the plurality of control lines and a first contact coupled to the plurality of first memory cells and a second contact coupled to the plurality of second memory cells.
47. The integrated circuit of claim 46, wherein the first select line and the second select line are arranged substantially in parallel to the plurality of control lines.
48. The integrated circuit of claim 35, wherein the first memory cells and the second memory cells comprise charge storing memory cells.
49. The integrated circuit of claim 48, wherein the first memory cells and the second memory cells comprise floating gate memory cells or charge trapping memory cells.
50. The integrated circuit of claim 35, wherein the first line is part of the first memory cell string and the second line is part of the second memory cell string.
51. The integrated circuit of claim 35, wherein the control gate region of the first switching element and the control gate region of the second switching element are self-aligned control gate regions with regard to the first line and the second line.
52. The integrated circuit of claim 35, wherein the control gate region of the first switching element and the control gate region of the second switching element have substantially the same gate length.
53. The integrated circuit of claim 35, further comprising:
a first select line contact coupling the first select line with the control gate region of the first switching element; and
a second select line contact coupling the second select line with the control gate region of the second switching element.
54. The integrated circuit of claim 53, wherein two adjacent switching elements are coupled with each other, wherein a first switching element of the two adjacent switching elements is coupled to the first select line contact and a second switching element of the two adjacent switching elements is coupled to the second select line contact and wherein the two adjacent switching elements are of the same type of switching element.
55. The integrated circuit of claim 53, wherein the first select line contact and the second select line contact are directly connected with a conductive structure of a metallization plane.
56. The integrated circuit of claim 35, further comprising:
a first contact to contact the plurality of first memory cells; and
a second contact to contact the plurality of second memory cells.
57. The integrated circuit of claim 56, further comprising:
a plurality of third memory cells arranged along a third line adjacent to the plurality of first memory cells;
a plurality of fourth memory cells arranged along a fourth line adjacent to the plurality of second memory cells;
wherein the first contact is coupled to the plurality of first memory cells and the plurality of third memory cells; and
wherein the second contact is coupled to the plurality of fourth memory cells and the plurality of second memory cells.
58. The integrated circuit of claim 57, wherein the first contact and the second contact are arranged laterally offset to one another.
59. The integrated circuit of claim 35,
wherein the control gate regions of the switching elements are floating gate regions; and
wherein each of the switching elements further comprises an additional control gate region, that is electrically coupled to the corresponding floating gate region.
60. The integrated circuit of claim 46, wherein the first contact and the second contact are arranged relative to one another such that they have substantially no overlap in a direction that is substantially perpendicular to the first line or the second line.
61. An integrated circuit, comprising:
a memory cell field comprising a plurality of groups of non-volatile memory cells, wherein each group of non-volatile memory cells is arranged along a respective line;
a plurality of contacts, each contact being coupled to a respective group of non-volatile memory cells;
a plurality of select lines crossing the lines; and
a plurality of switching elements, wherein the switching element are coupled to a respective group of non-volatile memory cells;
wherein each contact is coupled to a respective select line such that a regular alternating coupling pattern is provided between the contacts and the select lines.
62. The integrated circuit of claim 61, wherein each contact is coupled to a respective select line such that respective adjacent contacts are coupled with different select lines.
63. The integrated circuit of claim 61, wherein the lines are substantially parallel to each other.
64. A method for manufacturing an integrated circuit, the method comprising:
forming a plurality of first memory cells arranged along a first line;
forming a plurality of second memory cells arranged along a second line;
forming a plurality of switching elements, wherein a first switching element is coupled to the first memory cells and a second switching element is coupled to the second memory cells;
forming a first select line crossing the first line and the second line; and
forming a second select line crossing the first line and the second line;
wherein the first switching element is formed such that it comprises a control gate region that comprises a portion overlapping the first select line and a portion overlapping the second select line, wherein the control gate region extends along the first line;
wherein the second switching element is formed such that it comprises a control gate region that comprises a portion overlapping the first select line and a portion overlapping the second select line, wherein the control gate region extends along the second line.
65. The method of claim 64, wherein the first memory cells and the second memory cells are formed as non-volatile memory cells.
66. The method of claim 64,
wherein the plurality of first memory cells are serially source-to-drain coupled, thereby forming a first memory cell string; and
wherein the plurality of second memory cells are serially source-to-drain coupled, thereby forming a second memory cell string.
67. The method of claim 64, further comprising forming a plurality of control lines to control the first memory cells and the second memory cells.
68. The method of claim 67, wherein the first select line and the second select line are arranged between the plurality of control lines and a first contact being coupled to the plurality of first memory cells and a second contact being coupled to the plurality of second memory cells.
69. The method of claim 64, wherein the control gate region of the first switching element and the control gate region of the second switching element are formed as self-aligned control gate regions.
70. The method of claim 69, wherein the control gate region of the first switching element and the control gate region of the second switching element are formed self-aligned with regard to the first line and the second line.
71. The method of claim 64, wherein the control gate region of the first switching element and the control gate region of the second switching element are formed such that they have substantially the same gate length.
72. The method of claim 64, further comprising:
forming a first select line contact coupling the first select line with the control gate region of the first switching element; and
forming a second select line contact coupling the second select line with the control gate region of the second switching element.
73. A method for manufacturing an integrated circuit, the method comprising:
forming a memory cell field comprising a multiplicity of groups of non-volatile memory cells, wherein each group of non-volatile memory cells comprises a plurality of non-volatile memory cells, wherein each group of non-volatile memory cells is arranged along a respective line;
forming a plurality of contacts, each contact being coupled to a respective group of non-volatile memory cells;
forming a plurality of select lines crossing the first line and the second line; and
forming a plurality of switching elements, wherein the switching element are coupled to a respective group of non-volatile memory cells;
wherein each contact is coupled to a respective select line such that a regular alternating coupling pattern is provided between the contacts and the select lines.
74. A memory module, comprising:
a plurality of integrated circuits arranged as a module, wherein at least one integrated circuit of the multiplicity of integrated circuits comprises:
a plurality of first memory cells arranged along a first line;
a plurality of second memory cells arranged along a second line;
a plurality of switching elements, wherein a first switching element is coupled to the first memory cells and a second switching element is coupled to the second memory cells;
a first select line crossing the first line and the second line; and
a second select line crossing the first line and the second line;
wherein the first switching element comprises a control gate region which comprises a portion overlapping the first select line and a portion overlapping the second select line, wherein the control gate region extends along the first line;
wherein the second switching element comprises a control gate region which comprises a portion overlapping the first select line and a portion overlapping the second select line, wherein the control gate region extends along the second line.
75. The memory module of claim 74, wherein the memory module is a stackable memory module in which at least some of the integrated circuits are stacked one above the other.
76. A computing system, comprising:
a processing apparatus
an input apparatus coupled to the processing apparatus;
an output apparatus coupled to the processing apparatus; and
a memory cell arrangement coupled to the processing apparatus, the memory cell arrangement comprising:
a plurality of first memory cells arranged along a first line;
a plurality of second memory cells arranged along a second line;
a plurality of switching elements, wherein a first switching element is coupled to the first memory cells and a second switching element is coupled to the second memory cells;
a first select line crossing the first line and the second line; and
a second select line crossing the first line and the second line;
wherein the first switching element comprises a control gate region which comprises a portion overlapping the first select line and a portion overlapping the second select line, wherein the control gate region extends along the first line;
wherein the second switching element comprises a control gate region which comprises a portion overlapping the first select line and a portion overlapping the second select line, wherein the control gate region extends along the second line.
77. An integrated circuit, comprising:
a plurality of first memory cells arranged along a first line;
a first contact to contact the plurality of first memory cells;
a plurality of second memory cells arranged along a second line; and
a second contact to contact the plurality of second memory cells;
wherein the first contact and the second contact are arranged relative to one another such that they have substantially no overlap in a direction that is substantially perpendicular to the first line or the second line.
78. The integrated circuit of claim 77,
wherein the plurality of first memory cells are serially source-to-drain coupled, thereby forming a first memory cell string;
wherein the first contact contacts a portion of the serial coupling of the first memory cell string;
wherein the plurality of second memory cells are serially source-to-drain coupled, thereby forming a second memory cell string; and
wherein the second contact contacts a portion of the serial coupling of the second memory cell string.
79. An integrated circuit, comprising:
a plurality of first memory cells arranged along a first line;
a plurality of second memory cells arranged along a second line;
a first contact coupled to the plurality of first memory cells and the plurality of second memory cells;
a plurality of third memory cells arranged along a third line;
a plurality of fourth memory cells arranged along a fourth line; and
a second contact coupled to the plurality of third memory cells and the plurality of fourth memory cells;
wherein the first contact and the second contact are arranged relative to one another such that they have substantially no overlap in a direction that is substantially perpendicular to at least one of the four lines.
80. The integrated circuit of claim 79, further comprising:
a first group of a plurality of switching elements, wherein two adjacent switching elements are coupled with each other, wherein a first switching element of the two adjacent switching elements is coupled to the first contact and a second switching element of the two adjacent switching elements is coupled to the second contact, wherein the first switching element and the second switching element are of a first type of switching element; and
a second group of a plurality of switching elements, wherein two adjacent switching elements are coupled with each other, wherein a third switching element of the two adjacent switching elements is coupled to the third contact and a fourth switching element of the two adjacent switching elements is coupled to the fourth contact, wherein the third switching element and the fourth switching element are of a second type of switching element, which is different from the first type of switching element;