1. A dishwashing machine comprising:
a tub configured to define a washing space;
an upper rack and a lower rack disposed in the tub and configured to receive objects to be washed;
a lower arm disposed at a lower side of the lower rack and configured to spray wash water to the lower rack;
a rack fixing unit provided at the lower rack;
a tower nozzle fixed to the rack fixing unit and configured to spray wash water to the upper rack; and
a tower connection unit provided in the lower arm and configured to move from the lower arm based on water pressure in the lower arm, the tower connection unit being connected to the tower nozzle to supply wash water to the tower nozzle based on the tower connection unit being moved from the lower arm,
wherein the rack fixing unit comprises a guide to guide movement of the tower connection unit from the lower arm to the tower nozzle.
2. The dishwashing machine according to claim 1, wherein the rack fixing unit comprises:
a rack fixing body removably fixed to the lower rack, the rack fixing body having a fixing body through hole that communicates with the tower nozzle; and
a removable pipe coupling unit provided in the fixing body through hole, the removable pipe coupling unit having a removable pipe receiving hole through which an outer circumference of the tower connection unit is inserted.
3. The dishwashing machine according to claim 2, wherein the guide comprises a first inclined surface provided at the fixing body through hole such that the first inclined surface is inclined to the removable pipe receiving hole.
4. The dishwashing machine according to claim 3, wherein the guide further comprises a second inclined surface provided at the removable pipe coupling unit such that the second inclined surface is connected to the first inclined surface, the second inclined surface being inclined to the removable pipe receiving hole.
5. The dishwashing machine according to claim 1, wherein the rack fixing unit comprises:
a rack fixing body removably fixed to the lower rack, the rack fixing body having a fixing body through hole that communicates with the tower nozzle; and
a removable pipe coupling unit movably provided in the fixing body through hole to facilitate connection between the tower connection unit and the tower nozzle even when a center of the tower connection unit is not aligned with a center of the tower nozzle.
6. The dishwashing machine according to claim 5:
wherein the rack fixing body further comprises a flange location groove concavely bent toward the fixing body through hole, and
wherein the removable pipe coupling unit comprises a coupling unit body inserted through the fixing body through hole, a removable pipe receiving hole, through which an outer circumference of the tower connection unit is inserted, and a coupling unit flange provided at an outer circumference of the coupling unit body such that the coupling unit flange is supported in the flange location groove.
7. The dishwashing machine according to claim 6:
wherein the coupling unit body has a diameter less than a diameter of the fixing body through hole, and
wherein the coupling unit flange has a diameter greater than the diameter of the fixing body through hole and less than a diameter of the flange location groove.
8. The dishwashing machine according to claim 7, wherein the guide comprises an inclined surface provided at the coupling unit body such that the inclined surface is inclined to the removable pipe receiving hole.
9. The dishwashing machine according to claim 8, wherein the removable pipe coupling unit further comprises a sealing unit provided in the removable pipe receiving hole such that the sealing unit contacts the outer circumference of the tower connection unit.
10. The dishwashing machine according to claim 9:
wherein the sealing unit is formed of an elastic material, and
wherein the sealing unit further comprises:
a sealing unit through hole in which the outer circumference of the tower connection unit is received; and
a plurality of protrusions provided at the sealing unit through hole such that the protrusions are arranged at predetermined intervals.
11. The dishwashing machine according to claim 1, further comprising:
a water supply pump configured to supply wash water,
wherein the in the lower arm is caused by operation of the water supply pump.
12. The dishwashing machine according to claim 11, wherein the tower connection unit is configured to disconnect from the tower nozzle and move to the lower arm based on a reduction in water pressure on the tower connection unit caused by discontinuing operation of the water supply pump.
13. The dishwashing machine according to claim 1, wherein the tower connection unit is configured to alternate between connecting water supply to the tower nozzle and connecting water supply to the lower arm each time the tower connection unit moves from the lower arm.
14. The dishwashing machine according to claim 1, wherein the tower connection unit is configured to rotate each time the tower connection unit moves from the lower arm and connects to the tower nozzle and each time the tower connection unit disconnects from the tower nozzle and moves to the lower arm.
15. The dishwashing machine according to claim 14, wherein the tower connection unit is configured to, at a first angle of rotation, connect water supply to the tower nozzle and block water supply to the lower arm and, at a second angle of rotation that is different than the first angle of rotation, connect water supply to the lower arm and block water supply to the tower nozzle.
16. A dishwashing machine comprising:
a tub configured to define a washing space;
an upper rack and a lower rack disposed in the tub and configured to receive objects to be washed;
a lower arm comprising a lower arm chamber, into which wash water is introduced, a removable pipe chamber communicating with the lower arm chamber via a chamber communication hole, and an arm channel communicating with the lower arm chamber via an arm channel communication hole, the arm channel being configured to spray wash water to the lower rack;
a rack fixing unit provided at the lower rack;
a tower nozzle fixed to the rack fixing unit and configured to spray wash water to the upper rack; and
a tower connection unit provided in the removable pipe chamber, the tower connection unit being moved from the removable pipe chamber and connected to the tower nozzle based on water pressure in the removable pipe chamber,
wherein the rack fixing unit comprises a guide configured to guide movement of the tower connection unit from the removable pipe chamber to the tower nozzle.
17. The dishwashing machine according to claim 16, further comprising:
a water supply pump configured to supply wash water to the lower arm chamber; and
a channel change unit provided in the lower arm chamber and configured to alternately open the chamber communication hole and the arm channel communication hole depending upon water pressure in the lower arm chamber controlled by the water supply pump.
18. The dishwashing machine according to claim 17, wherein the channel change unit comprises:
a change unit body configured to reciprocate and rotate in the lower arm chamber depending upon the water pressure in the lower arm chamber, the change unit body having a chamber opening hole configured to open the chamber communication hole depending upon a rotational angle of the change unit body and an arm channel opening hole configured to open the arm channel communication hole depending upon the rotational angle of the change unit body.
19. The dishwashing machine according to claim 18:
wherein the lower arm chamber further comprises an introduction hole, through which wash water is introduced, a lower gear engagement unit provided to surround the introduction hole, and an upper gear engagement unit provided at an upper side of the lower arm chamber, and
wherein the channel change unit further comprises:
an upper gear provided at a top of the change unit body such that the upper gear is engaged with the upper gear engagement unit and rotates the change unit body such that, based on the upper gear being coupled to the upper gear engagement unit, the chamber opening hole opens the chamber communication hole or the arm channel opening hole opens the arm channel communication hole; and
a lower gear provided at a bottom of the change unit body such that the lower gear is engaged with the lower gear engagement unit and rotates the change unit body such that, based on the lower gear being coupled to the lower gear engagement unit, the chamber opening hole opens the chamber communication hole or the arm channel opening hole opens the arm channel communication hole.
20. The dishwashing machine according to claim 19, wherein the upper gear and the lower gear are configured to alternately rotate the change unit body such that the chamber opening hole opens the chamber communication hole a first instance in which the upper gear is coupled to the upper gear engagement unit and the arm channel opening hole opens the arm channel communication hole a second instance in which the upper gear is coupled to the upper gear engagement unit, the second instance immediately following the first instance.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A system to test integrated circuits on a wafer, comprising:
a transceiver formed on the wafer; and
an antenna system couplable to the transceiver.
2. The system of claim 1, wherein the transceiver is couplable to a plurality of integrated circuits formed on the wafer to test selected ones of the plurality of integrated circuits.
3. The system of claim 2, wherein the transceiver is adapted to apply test signals to at least one selected integrated circuit of the plurality of integrated circuits to test the at least one selected integrated circuit in response to the antenna system receiving a signal.
4. The system of claim 2, wherein the antenna system is adapted to transmit signals corresponding to results from testing at least one selected integrated circuit of the plurality of integrated circuits.
5. The system of claim 2, further comprising a multiplexing circuit to couple the transceiver to each of the plurality of integrated circuits.
6. The system of claim 1, wherein the antenna system comprises one of a loop antenna, a pair of dipole antennas or an antenna array formed by loop or dipole antenna elements.
7. The system of claim 1, further comprising:
a plurality of transceivers, each adapted to receive and transmit signals to test selected ones of a multiplicity of integrated circuits formed on the wafer and each of the transceivers being formed at a different location on the wafer; and
a plurality of antenna systems, each antenna system being coupleable to at least one of the plurality of transceivers and each of the plurality of antenna systems being formed at different locations on the wafer.
8. The system of claim 7, wherein each transceiver of the plurality of transceivers or each transceiver in a subset of transceivers of the plurality of transceivers are each adapted to transmit test result signals simultaneously on different radio frequencies.
9. The system of claim 7, wherein each of the antenna systems is formed to minimize electromagnetic interference with the multiplicity of integrated circuits during testing.
10. The system of claim 7, wherein each of the transceivers and antenna systems are formed in a predetermined distribution on the wafer.
11. The system of claim 10, wherein the predetermined distribution is adapted to minimize space utilization, facilitate optimum testing of a selected number of integrated circuits simultaneously, and to minimize electromagnetic interference with the integrated circuits during testing and between different transceivers and associated antenna systems.
12. The system of claim 7, further comprising a multiplexing circuit, wherein an integrated circuit to be test and an associated transceiver are selectable by at least one of a word-line or a bit-line and wherein the transceiver is adapted to select a proper stream of test data of the integrated circuit under test from the multiplexing circuit.
13. The system of claim 7, further comprising a word-linebit-line power distribution scheme adapted to select an integrated circuit to be tested and an associated transceiver and to distribute test mode power to the selected integrated circuit to be tested and the associated transceiver.
14. The system of claim 1, wherein the transceiver receives power via one of a probe, a radio frequency power signal, a word-line or a bit-line, and a pad electrically connectable to the transceiver, wherein the pad is connectable to an external power source.
15. The system of claim 1, further comprising a pad formed proximate to a periphery of the wafer and electrically connectable to the transceiver to provide power to the transceiver.
16. The system of claim 1, further comprising another transceiver and test unit external to the wafer and adapted to transmit scan test vectors to the transceiver on the wafer and to receive test results from the transceiver on the wafer.
17. The system of claim 16, wherein the transceiver is adapted to transmit self-test data and to receive and transmit scan test vectors from the external transceiver and test unit.
18. The system of claim 1, wherein the transceiver is adapted to provide one of an amplitude shift keying (ASK) or an on-off keying (OOK) modulation scheme.
19. The system of claim 1, wherein the transceiver is adapted to receive and to transmit signals to perform real-time tests periodically during fabrication of the wafer.
20. The system of claim 1, wherein the transceiver is adapted receive and to transmit signals to perform tests under burn-in stress conditions or other environmental extremes.
21. The system of claim 1, wherein the transceiver comprises:
a down converter to convert a received radio frequency (RF) signal to an intermediate frequency (IF) signal;
a received signal strength indicator (RSSI);
a limiting amplifier to amplify the IF signal in response to the RSSI; and
a comparator to generate a data signal in response to the amplified IF signal.
22. The system of claim 1, wherein the transceiver comprises:
a phasefrequency detector to receive an input or reference signal;
a charge pump to receive an output signal from the phasefrequency detector;
a filter to filter selected frequency band signals from a charge pump signal;
a voltage controlled oscillator to receive a filtered signal from the filter; and
a power amplifier to modulate a carrier signal from the voltage controlled oscillator by a data input signal.
23. The system of claim 1, wherein the transceiver is formed in one of a scribe line formed in the wafer, on a chip of each integrated circuit, on another chip on the wafer not used to form an integrated circuit, or on an unusable portion of the wafer.
24. The system of claim 1, wherein the antenna system comprises an antenna system formed in at least one of a same scribe line as the transceiver, in at least one other scribe line formed in the wafer, on a chip on the wafer not used to form an integrated circuit or on an usable portion of the wafer.
25. The system of claim 24, wherein the antenna system comprises:
a loop antenna adapted to be shared by a plurality of transceivers; and
a plurality of differential amplifier circuits, each differential amplifier circuit being associated with one of the plurality of transceivers, wherein only one of the plurality of differential amplifier circuits is active at any given time to permit the associated transceiver to receive or transmit signals.
26. The system of claim 24, wherein the antenna system further comprises an inductor connected in parallel with each differential amplifier circuit, wherein the inductor completes the loop antenna when an associated differential amplifier circuit is disabled.
27. The system of claim 24, wherein the antenna system further comprises:
a pair of inductors connected in parallel with each differential amplifier circuit, wherein the pair of inductors complete the loop antenna when an associated differential amplifier circuit is disabled; and
a field effect transistor (FET) to couple a voltage source to a node between each pair of inductors, wherein the voltage source is connected to the node in response to an RF carrier signal from an associated one of the plurality of transceivers being applied to a gate of the FET.
28. The system of claim 1, wherein the antenna system comprises an antenna external to the wafer and wherein the transceiver is connectable to the antenna by a wafer boat or fixture.
29. The system of claim 1, further comprising:
an insulative layer formed on the wafer; and
a conductive layer formed on the insulative layer and electrically connecting to the transceiver via an opening formed in the insulative layer to test selected ones of the integrated circuits during manufacturing, wherein the insulative layer and the conductive layer are removable for further fabrication of the integrated circuits.
30. A system to test integrated circuits on a wafer, comprising:
a plurality of transceivers each adapted to receive and transmit signals to test selected ones of a multiplicity of integrated circuits formed on the wafer and each of the transceivers being formed at a different location on the wafer in one of a plurality of scribe lines formed in the wafer or at other locations on the wafer; and
at least one antenna systems couplable to the plurality of transceivers.
31. The system of claim 30, further comprising a multiplexing circuit to couple each transceiver selectively to one of a predetermined number of the multiplicity of integrated circuits.
32. The system of claim 30, wherein each transceiver of the plurality of transceivers or each transceiver in a subset of transceivers of the plurality of transceivers are each adapted to transmit signals corresponding to test results simultaneously on different radio frequencies.
33. The system of claim 30, wherein each of the transceivers and associated antenna systems are formed in a predetermined distribution on the wafer.
34. The system of claim 30, further comprising a word-linebit-line distribution scheme adapted to select each integrated circuit to be tested and an associated transceiver.
35. The system of claim 30, wherein each transceiver is powered via one of a probe, a radio frequency power signal, a word-linebit-line power distribution scheme and a pad electrically connectable to the transceiver, wherein the pad is connectable to an external power source.
36. The system of claim 30, wherein each transceiver comprises:
a down converter to convert a received radio frequency (RF) signal to an intermediate signal (IF);
a received signal strength indicator (RSSI);
an amplifier to amplify the IF signal in response to the RSSI; and
a comparator to generate a data signal in response to the amplified IF signal.
37. The system of claim 30, wherein each transceiver comprises:
a phasefrequency detector to receive an input or reference signal;
a charge pump to receive an output signal from the phasefrequency detector;
a filter to filter signals in a selected frequency band from the charge pump;
a voltage controlled oscillator to receive a filtered signal from the filter; and
a power amplifier to modulate a carrier signal from the voltage controlled oscillator by a data signal.
38. The system of claim 30, wherein the at least one antenna system comprises an antenna external to the wafer and wherein each of the plurality of transceivers is connectable to the antenna by a wafer boat or fixture.
39. The system of claim 30, further comprising a plurality of antenna systems, each antenna system being coupleable to at least one of the plurality of transceivers and each of the plurality of antenna systems being formed at different locations on the wafer in at least one of the plurality of scribe lines.
40. The system of claim 39, wherein each antenna system comprises one of a loop antenna, a pair of dipole antennas or an antenna array formed by loop or dipole antenna elements.
41. The system of claim 39, wherein each antenna system comprises:
a loop antenna adapted to be shared by a predetermined number of the plurality of transceivers; and
a plurality of differential amplifiers, each differential amplifier being associated with one of the predetermined number of transceivers, wherein only one of the plurality of differential amplifiers is active at any given time to permit the associated transceiver to receive or transmit signals.
42. The system of claim 30, further comprising:
an insulative layer formed on the wafer; and
a conductive layer formed on the insulative layer in line traces electrically connecting to each of the plurality of transceivers via openings formed in the insulative layer to test selected ones of the integrated circuits during manufacturing, wherein the insulative layer and the conductive layer are removable for further fabrication of the integrated circuits.
43. A transceiver to test integrated circuits on a wafer, comprising:
a down converter to convert a received radio frequency (RF) signal to an intermediate frequency (IF) signal;
a received signal strength indicator (RSSI);
an amplifier to amplify the IF signal in response to the RSSI; and
a comparator to generate a data signal in response to the amplified IF signal.
44. The transceiver of claim 43, wherein each of the down converter, RSSI, amplifier and comparator are formed in a scribe line formed in the wafer.
45. The transceiver of claim 43, further comprising:
a phasefrequency detector to receive an input or reference signal;
a charge pump to receive an output signal from the phasefrequency detector;
a filter to filter signals in a selected frequency band from the charge pump;
a voltage controlled oscillator to receive a filtered signal from the filter; and
a power amplifier to modulate a carrier signal from the voltage controlled oscillator.
46. The transceiver of claim 45, wherein each of the phasefrequency detector, charge pump, filter, voltage controlled oscillator and power amplifier are formed in a scribe line formed in the wafer.
47. An antenna system to test integrated circuits on a wafer, comprising:
a loop antenna adapted to be shared by a plurality of transceivers; and
a plurality of differential amplifier circuits, each differential amplifier circuit being associated with one of the plurality of transceivers, wherein only one of the plurality of differential amplifier circuits is active at any given time to permit the associated transceiver to receive or transmit signals.
48. The antenna system of claim 47, wherein each of the loop antenna and the plurality of differential amplifier circuits are formed in at least one scribe line formed in the wafer.
49. The antenna system of claim 47, wherein the antenna system further comprises at least one inductor connected in parallel with each differential amplifier circuit, wherein the at least one inductor completes the loop antenna when an associated differential amplifier circuit is disabled.
50. The antenna system of claim 47, further comprising:
a pair of inductors connected in parallel with each differential amplifier circuit, wherein the pair of inductors complete the loop antenna when an associated differential amplifier circuit is disabled; and
a field effect transistor (FET) to couple a voltage source to a node between each pair of inductors, wherein the voltage source is connected to the node in response to an RF carrier signal from an associated one of the plurality of transceivers being applied to a gate of the FET.
51. The antenna system of claim 47, wherein the loop antenna is physically small compared to a wavelength at which the loop antenna operates.
52. A method of making a system to test integrated circuits on a wafer, comprising:
forming a transceiver on the wafer; and
providing an antenna system couplable to the transceiver.
53. The method of claim 52, wherein forming the transceiver comprises forming the transceiver in one of a scribe line, on a chip or on an unusable portion of the wafer.
54. The method of claim 52, further comprising forming a multiplexing circuit to couple the transceiver to each of a plurality of integrated circuits.
55. The method of claim 52, further comprising:
forming a plurality of transceivers, each adapted to receive and transmit signals to test selected ones of a multiplicity of integrated circuits formed on the wafer and each of the transceivers being formed at different location on the wafer in one of a plurality of scribe lines formed in the wafer; and
forming a plurality of antenna systems, each antenna system being coupleable to at least one of a plurality of transceivers and each of the plurality of antennas systems being formed at different locations on the wafer in at least one of a plurality of scribe lines.
56. The method of claim 55, further comprising forming each of the transceivers and associated antenna systems in a predetermined distribution on the wafer.
57. The method of claim 55, wherein forming each transceiver comprises:
forming a down converter to convert a received radio frequency (RF) signal to an intermediate (IF) signal;
forming a received signal strength indicator (RSSI);
forming an amplifier to amplify the IF signal in response to the RSSI; and
forming a comparator to generate a data signal in response to the amplified IF signal.
58. The method of claim 55, wherein forming each transceiver comprises:
forming a phasefrequency detector to receive an input or reference signal;
forming a charge pump to receive an output signal from the phasefrequency detector;
forming a filter to filter signals in a selected frequency band from the charge pump;
forming a voltage controlled oscillator to receive a filtered signal from the filter; and
forming a power amplifier to modulate a carrier signal from the voltage controlled oscillator by a data signal.
59. The method of claim 55, wherein forming each antenna system comprises forming one of a loop antenna, a pair of dipole antennas or an antenna array formed by loop or dipole antenna elements.
60. The method of claim 55, wherein forming each antenna system comprises:
forming a loop antenna adapted to be shared by a predetermined number of the plurality of transceivers; and
forming a plurality of differential amplifier circuits, each differential amplifier circuit being associated with one of the predetermined number of transceivers, wherein only one of the plurality of differential amplifier circuits is active at any given time to permit the associated transceiver to receive or transmit signals.
61. A method to test integrated circuits on a wafer, comprising:
selecting at least one integrated circuit of a plurality of integrated circuits to be tested;
performing a test or self-test on the at least one selected integrated circuit in response to selecting the at least one integrated circuit; and
transmitting test results via a transceiver associated with the at least one selected integrated circuit.
62. The method of claim 61, wherein selecting the at least one integrated circuit comprises using a word-linebit-line distribution.
63. The method of claim 61, further comprising transmitting test results of the at least one selected integrated circuit to an external transceiver.
64. The method of claim 61, wherein transmitting the test results comprises transmitting in one of an amplitude shift keying (ASK) or an on-off keying (OOK) modulation scheme.
65. The method of claim 61, wherein the transceiver is formed in one of a scribe line in the wafer, on a chip or on an unusable portion of the wafer.
66. The method of claim 61, further comprising applying power to the at least one selected integrated circuit via one of a probe, radio frequency power signal, a pad electrically connectable to an external power source, a word-line or a bit-line.
67. The method of claim 61, further comprising applying power to the transceiver associated with the at least one selected integrated circuit via one of a probe, radio frequency power signal, a pad electrically connectable to an external power source, a word-line or a bit-line.
68. The method of claim 61, further comprising receiving and transmitting signals to perform real-time tests of the at least one selected integrated circuit during at least one of fabrication and burn-in of the wafer.
69. The method of claim 61, further comprising transmitting an RF signal to a transceiver associated with the at least one selected integrated circuit to test the integrated circuit.
70. The method of claim 61, further comprising:
forming an insulative layer on the wafer; and
forming a conductive layer on the insulative layer in line traces electrically connecting to each of a plurality of transceivers via openings formed in the insulative layer to test selected ones of the integrated circuits during manufacturing; and
removing the insulative layer and the conductive layer for further fabrication of the integrated circuits.