1. A method comprising:
allowing at least two software clients to use a connection to the Internet at the same time;
determining when both clients have released the connection; and
discontinuing the connection when both clients have released the connection.
2. The method of claim 1 including enabling said clients to connect to the Internet through a software layer and using the layer to accommodate at least two different types of Internet connections.
3. The method of claim 1 including monitoring the connection so that the connection is not released until all clients using the connection have released the connection.
4. The method of claim 1 including monitoring the connection for a connection failure.
5. The method of claim 1 including receiving a request from a client for a connection and determining whether a connection has already been established.
6. The method of claim 1 including providing a state machine having a busy state when the connection is being used by a client and an idle state when the connection is not being used by a client.
7. An article comprising a medium storing instructions that enable a processor-based system to:
allow at least two software clients to use a connection to the Internet at the same time;
determine when both clients have released the connection; and
discontinue the connection when both clients have released the connection.
8. The article of claim 7 further storing instructions that enable the processor-based system to enable the clients to connect to the Internet through a software layer and use the layer to accommodate at least two different types of Internet connections.
9. The article of claim 7 further storing instructions that enable the processor-based system to monitor the connection so that the connection is not released until all clients using the connection have released the connection.
10. The article of claim 7 further storing instructions that enable the processor-based system to monitor the connection for a connection failure.
11. The article of claim 7 further storing instructions that enable the processor-based system to receive a request from a client for a connection and to determine whether a connection has already been established.
12. The article of claim 7 further storing instructions that enable the processor-based system to implement a state machine having a busy state when a connection is being used by the client and an idle state when the connection is not being used by the client.
13. A system comprising:
a processor;
an interface to enable a connection to the Internet; and
a storage storing instructions that enable at least two software clients to use a connection to the Internet at the same time, determine when both clients have released the connection and discontinue the connection when both clients have released the connection.
14. The system of claim 13 wherein said storage stores instructions that enable the client to connect to the Internet through a software layer and use the layer to accommodate at least two different types of Internet connections.
15. The system of claim 13 wherein said storage stores instructions to enable the system to monitor the connection so that the connection will not be released until all clients using the connection have released the connection.
16. The system of claim 13 wherein said storage stores instructions to monitor the connection for a connection failure.
17. The system of claim 13 wherein said storage stores instructions to enable the system to receive a request from a client for a connection and to determine whether a connection has already been established.
18. The system of claim 13 wherein said storage stores instructions to implement a state machine having a busy state when a connection is being used by a client and an idle state when the connection is not being used by a client.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A method, comprising:
performing a hash-join operation in a hardware accelerator responsive to receiving, at a source comprising at least one database, a request to perform the hash join operation;
wherein performing the hash-join operation in the hardware accelerator comprises the steps of:
processing a first table comprising one or more rows;
hashing at least one join column in at least one of the one or more rows of the first table to set at least one bit in at least one bit vector;
storing in a memory of the hardware accelerator each of the rows of the first table hashing to the same hash value;
processing a second table comprising one or more rows;
hashing at least one join column in at least one of the one or more rows of the second table to generate at least one hash value;
probing the at least one bit vector using the at least one hash value; and
constructing a joined row responsive to the probing step;
wherein each of the rows of the first table hashing to the same hash value is stored in a separate memory bank of the memory at a first address corresponding to the hash value; and
wherein when a first memory bank of the memory is full, subsequent rows of the first table hashing to the bit vector corresponding to the first address are stored in a second memory bank at a second address, the second address being the next sequential address.
2. The method of claim 1, wherein the hardware accelerator is a field programmable gate array (FPGA).
3. The method of claim 1, wherein the first table is stored in a memory of the hardware accelerator.
4. The method of claim 1, wherein the at least one bit vector is stored in a memory of the hardware accelerator.
5. The method of claim 1, wherein the hashing, probing and row-construction steps are performed in a single pass through the second table.
6. The method of claim 1, wherein the row-construction step utilizes local predicate evaluation on the second table.
7. The method of claim 1, wherein at least one of the hashing steps is performed using hardware accelerated hashing.
8. The method of claim 1, wherein at least one of the hashing steps is performed using multiple hash functions.
9. The method of claim 8, wherein the multiple hash functions comprise a Bloom filter approach.
10. The method of claim 1, wherein two or more of the join columns in a row of at least one of the first table and the second table are hashed in parallel.
11. The method of claim 1, wherein two or more of the rows of at least one of the first table and the second table are hashed in parallel.
12. The method of claim 1, wherein the row-construction step is performed on one or more rows of the second table in parallel.
13. The method of claim 1, wherein the probing step further comprises determining if the bit position of the at least one hash value is set in at least one bit vector, and responsive to the determination selecting the row of the second table corresponding to the at least one hash value for the row-construction step.
14. The method of claim 13, wherein the row of the second table is evaluated using local predicates before being selected for the row-construction step.
15. The method of claim 1, wherein the step of processing a first table comprising one or more rows comprises processing two or more tables comprising one or more rows.
16. The method of claim 1, wherein the joined row is output to a memory.
17. A computer-readable storage medium comprising executable program code for implementing the method of claim 1.
18. An apparatus comprising:
a hardware accelerator comprising a matching unit and at least one memory bank, the hardware accelerator being operative to perform a hash-join operation responsive to receiving, at a source comprising at least one database, a request to perform the hash-join operation;
wherein the hardware accelerator is operative to perform the hash-join operation by:
processing a first table comprising one or more rows from a memory;
hashing at least one join column in at least one of the one or more rows of the first table to set at least one bit in at least one bit vector;
storing in memory banks of the hardware accelerator each of the rows of the first table hashing to the same hash value;
processing a second table comprising one or more rows from the memory;
hashing at least one join column in at least one of the one or more rows of the second table to generate at least one hash value;
probing the at least one bit vector using the at least one hash value;
constructing a joined row responsive to the probing step; and
outputting the joined row to the memory;
wherein each of the rows of the first table hashing to the same hash value is stored in a separate memory bank of the hardware accelerator at a first address corresponding to the hash value; and
wherein when a first memory bank of the hardware accelerator is full, subsequent rows of the first table hashing to the bit vector corresponding to the first address are stored in a second memory bank of the hardware accelerator at a second address, the second address being the next sequential address.
19. The apparatus of claim 18, wherein the hardware accelerator is a field programmable gate array (FPGA).
20. An apparatus comprising:
a processor coupled to a memory and operative to:
receive a request to perform a hash-join operation at a source comprising at least one database;
offload the request to perform the hash-join operation to a hardware accelerator; and
read a joined row from the memory;
wherein the joined row is constructed by the hardware accelerator;
wherein the hardware accelerator is operative to perform the hash-join operation by:
processing a first table comprising one or more rows from the memory;
hashing at least one join column in at least one of the one or more rows of the first table to set at least one bit in at least one bit vector;
storing in a hardware accelerator memory each of the rows of the first table hashing to the same hash value;
processing a second table comprising one or more rows from the memory;
hashing at least one join column in at least one of the one or more rows of the second table to generate at least one hash value;
probing the at least one bit vector using the at least one hash value;
constructing a joined row responsive to the probing step; and
outputting the joined row to the memory;
wherein each of the rows of the first table hashing to the same hash value is stored in a separate memory bank of the hardware accelerator memory at a first address corresponding to the hash value; and
wherein when a first memory bank of the hardware accelerator memory is full, subsequent rows of the first table hashing to the bit vector corresponding to the first address are stored in a second memory bank of the hardware accelerator at a second address, the second address being the next sequential address.