1. A semiconductor fabricating process, comprising:
providing a substrate having thereon a stacked structure and a mask layer disposed on the stacked structure;
forming an oxide layer on a surface of the mask layer and a surface of at least a portion of the stacked structure;
forming a first spacer on a sidewall of the stacked structure;
forming a second spacer on a sidewall of the first spacer;
performing a first etching process to remove the oxide layer on the surface of the mask layer; and
performing a second etching process to simultaneously remove the mask layer and the second spacer.
2. The semiconductor fabricating process as claimed in claim 1, wherein an etching rate of the oxide layer on the surface of the mask layer is larger than an etching rate of the second spacer in the first etching process.
3. The semiconductor fabricating process as claimed in claim 1, wherein an etching rate of the mask layer and the second spacer is larger than an etching rate of the first spacer in the second etching process.
4. The semiconductor fabricating process as claimed in claim 1, wherein a solution used in the first etching process comprises a hydrofluoric acid solution and a solution used in the second etching process comprises a phosphoric acid solution.
5. The semiconductor fabricating process as claimed in claim 1, wherein a material of the first spacer comprises silicon oxide.
6. The semiconductor fabricating process as claimed in claim 1, wherein a material of the second spacer comprises silicon nitride, silicon carbide, or silicon oxynitride.
7. The semiconductor fabricating process as claimed in claim 1, wherein the mask layer and the second spacer are formed by the same material.
8. The semiconductor fabricating process as claimed in claim 1, wherein a material of the mask layer comprises silicon nitride, silicon carbide, or silicon oxynitride.
9. The semiconductor fabricating process as claimed in claim 1, wherein the step of forming the oxide layer comprises performing a rapid thermal oxidation process.
10. The semiconductor fabricating process as claimed in claim 1, wherein the stacked structure is a gate structure.
11. The semiconductor fabricating process as claimed in claim 10, wherein the gate structure comprises a gate dielectric layer and a gate sequentially formed on the substrate.
12. The semiconductor fabricating process as claimed in claim 10, wherein the gate structure comprises a tunneling dielectric layer, a floating gate, an inter-gate dielectric layer, and a control gate sequentially formed on the substrate.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. An integrated circuit comprising:
an electrically conductive material possessing spontaneous magnetization;
an electrically resistive material possessing spontaneous magnetization;
wherein the electrical conductive material and the electrically resistive material do not contact each other;
a spacer comprising atomically unbound electrons to transfer spin between the electrically resistive material and the electrically conductive material;
a thermal barrier located at least partially between a first electrode and the electrically conductive material;
a second electrode located at least partially in a via hole through the electrically resistive material;
wherein the second electrode electrically couples the spacer to a transistor and the spacer is in electrical contact with the second electrode; and
a strip multiple times longer than the spacer, the strip being oriented perpendicular to a longitudinal direction of the spacer.
2. The integrated circuit of claim 1 wherein:
the electrically resistive material comprises a crystalline material having only electrons bound to atomic nuclei to constitute ions, the crystalline material lacking free electrons.
3. An integrated circuit comprising:
an electrically conductive material possessing spontaneous magnetization;
an electrically resistive material possessing spontaneous magnetization;
wherein the electrical conductive material and the electrically resistive material do not contact each other;
a spacer comprising atomically unbound electrons to transfer spin between the electrically resistive material and the electrically conductive material;
wherein the electrically resistive material comprises a crystalline material having only electrons bound to atomic nuclei to constitute ions, the crystalline material lacking free electrons; and
wherein the electrically resistive material further comprises an atomic monolayer in contact with the crystalline material, and the atomic monolayer comprises atomic nuclei with electrons having unbalanced spin; and
wherein the spacer is in direct contact with the electrically resistive material.
4. The integrated circuit of claim 1 further comprising:
a heating element located in thermal contact with at least one of the electrically resistive material, the electrically conductive material, and the spacer, the heating element being so positioned as to transfer heat at least between the spacer and the electrically resistive material.
5. The integrated circuit of claim 1 further comprising:
a heating element;
wherein the heating element comprises at least one of (a) tunnel barrier and (b) Joule-effect heater.
6. An integrated circuit comprising:
an electrically conductive material possessing spontaneous magnetization;
an electrically resistive material possessing spontaneous magnetization;
wherein the electrical conductive material and the electrically resistive material do not contact each other;
a spacer comprising atomically unbound electrons to transfer spin between the electrically resistive material and the electrically conductive material;
wherein the spacer is in direct contact with the electrically resistive material;
a heat sink having greater thermal conductance than the electrically resistive material;
wherein said heat sink is located in direct thermal contact with at least one of the electrically resistive material, the electrically conductive material and the spacer;
a thermal barrier having smaller thermal conductance than the electrically resistive material; and
a heating element in thermal contact with each of the thermal barrier and the electrically conductive material.
7. An integrated circuit comprising:
an electrically conductive material possessing spontaneous magnetization;
an electrically resistive material possessing spontaneous magnetization;
wherein the electrical conductive material and the electrically resistive material do not contact each other;
a spacer comprising atomically unbound electrons to transfer spin between the electrically resistive material and the electrically conductive material;
a heat sink having greater thermal conductance than the electrically resistive material;
wherein said heat sink is located in direct thermal contact with at least one of the electrically resistive material, the electrically conductive material and the spacer; and
a heating element located in thermal contact with at least one of the electrically resistive material, the electrically conductive material, and the spacer, the heating element being so positioned as to transfer heat at least between the spacer and the electrically resistive material;
wherein the electrically resistive material is located in direct contact with the spacer.
8. The integrated circuit of claim 1 wherein:
said strip is located sufficiently close to the electrically resistive material such that a direction of magnetization of the electrically resistive material is changed on passage of an electrical current through a set of strips including said strip.
9. The integrated circuit of claim 1 wherein:
the spacer comprises a metal; and
said metal is at least one of: copper, silver and gold.
10. The integrated circuit of claim 1 wherein:
the electrically resistive material comprises a cubic crystalline ferrimagnetic oxide or a hexagonal crystalline ferrimagnetic oxide.
11. The integrated circuit of claim 1 wherein any ion in a ferrimagnetic oxide which gives up an electron to an oxygen atom is hereinafter referred to as a magnetic ion, wherein:
the electrically resistive material comprises a cubic crystalline ferrimagnetic oxide and an outer electron shell of each magnetic ion in said cubic crystalline ferrimagnetic oxide has five 3d electrons or seven 4f electrons.
12. The integrated circuit of claim 3 wherein:
the electrically resistive material comprises at least one of: meghamite \u03b3Fe2O3, nickel ferrite NiFe2O4, manganese-magnesium ferrite (Mn,Mg)Fe2O4, lithium-iron ferrite Li0.5 Fe2.5O4, lithium-zinc ferrite (Li,Zn,Fe)3O4, yttrium iron garnet Y3Fe5O12, yttrium-gadolimium iron garnet (Y,Gd)3Fe5O12, barium hexaferrite BaFe12O19, barium gadolinium-iron hexaferrite Ba(Gd, Fe)12O19, and aluminum-iron hexaferrite Ba(Fe, Al)12O19.
13. The integrated circuit of claim 1 wherein:
the spacer is located between the electrically conductive material and the electrically resistive material.
14. The integrated circuit of claim 1 further comprising:
a heat sink having greater thermal conductance than the electrically resistive material;
said heat sink being located in direct thermal contact with at least one of the electrically resistive material, the electrically conductive material and the spacer.
15. The integrated circuit of claim 1 wherein:
said strip comprises a metal.
16. A method comprising:
transferring heat in a structure to change a first direction of magnetization of an electrically conductive magnet to a second direction of magnetization;
wherein the structure comprises said electrically conductive magnet separated from a electrically resistive magnet by a spacer;
wherein prior to said transferring heat, the electrically conductive magnet has said first direction of magnetization;
wherein the heat is transferred between at least the spacer and the electrically resistive magnet;
wherein subsequent to said transferring heat, the electrically conductive magnet has said second direction of magnetization different from the first direction of magnetization;
wherein a majority of the heat that flows between at least the spacer and the electrically resistive magnet flows without an externally-added electrical current flowing therebetween; and
sensing said second direction of magnetization of the electrically conductive magnet.
17. The method of claim 16 wherein said transferring comprises:
generating said heat by passing current through a heating element in the structure;
wherein said heating element is comprised in or in direct thermal contact with at least one of the electrically conductive magnet, the spacer, and the electrically resistive magnet.
18. The method of claim 16 wherein:
said sensing comprises measuring voltage for a predetermined current; and
said voltage is measured across at least the electrically conductive magnet and the spacer.
19. The method of claim 16 further comprising:
passing an electrical current through an electrically conductive strip located adjacent to the electrically resistive magnet, so as to generate a magnetic field that changes a direction of magnetization of the electrically resistive magnet.
20. The method of claim 16 wherein:
said second direction of magnetization of the electrically conductive magnet sensed by said sensing is different from another direction of magnetization of the electrically resistive magnet prior to said transferring heat.
21. The method of claim 16 wherein:
said sensing comprises using a magnetic tunneling junction.
22. The method of claim 16 further comprising:
passing simultaneous electrical currents through a plurality of electrically conductive strips parallel to one another and located adjacent to the electrically resistive magnet, so as to generate a magnetic field that changes a direction of magnetization of the electrically resistive magnet.
23. The method of claim 16 wherein:
the heat is transferred continuously to keep a spin moment vector of the electrically conductive magnet in precession in an oscillator.
24. The integrated circuit of claim 3 further comprising:
a heat sink having greater thermal conductance than the electrically resistive material;
said heat sink being located in direct thermal contact with at least one of the electrically resistive material, the electrically conductive material and the spacer.
25. The integrated circuit of claim 3 further comprising:
a heating element so positioned as to transfer heat at least between the spacer and the electrically resistive material.
26. The integrated circuit of claim 25 wherein:
the heating element comprises at least one of (a) tunnel barrier and (b) Joule-effect heater.
27. The integrated circuit of claim 6 wherein:
the electrically resistive material comprises an atomic monolayer, the atomic monolayer comprising atomic nuclei with electrons having unbalanced spin.
28. The integrated circuit of claim 27 wherein:
each of a plurality of atoms in the atomic monolayer has a partially-filled 3d electron shell.
29. The integrated circuit of claim 7 wherein:
the direct contact of the spacer is with the atomic monolayer comprised in the electrically resistive material.
30. The integrated circuit of claim 29 wherein:
each of a plurality of atoms in the atomic monolayer has a partially-filled 3d electron shell.
31. The integrated circuit of claim 3 wherein:
the electrically resistive material has an electrical conductance therethrough that is multiple orders of magnitude lower relative to the electrical conductance through the electrically conductive material.
32. The integrated circuit of claim 6 wherein:
the electrically resistive material has an electrical conductance therethrough that is multiple orders of magnitude lower relative to the electrical conductance through the electrically conductive material.
33. The integrated circuit of claim 7 wherein:
the electrically resistive material has an electrical conductance therethrough that is multiple orders of magnitude lower relative to the electrical conductance through the electrically conductive material.
34. The integrated circuit of claim 1 wherein:
the electrically resistive material has an electrical conductance therethrough that is multiple orders of magnitude lower relative to the electrical conductance through the electrically conductive material.
35. The method of claim 16 wherein:
the electrically resistive magnet has an electrical conductance therethrough that is multiple orders of magnitude lower relative to the electrical conductance through the electrically conductive magnet.
36. The integrated circuit of claim 6 wherein:
the electrically resistive material has an electrical conductance that is sufficiently negligible to ensure that a majority of heat energy, when transferred between the spacer and the electrically resistive material, is carried by magnons rather than by electron movement.
37. The integrated circuit of claim 7 wherein:
the electrically resistive material has an electrical conductance that is sufficiently negligible to ensure that a majority of heat energy, when transferred between the spacer and the electrically resistive material, is carried by magnons rather than by electron movement.
38. The integrated circuit of claim 1 wherein:
the electrically resistive material has an electrical conductance that is sufficiently negligible to ensure that a majority of heat energy, when transferred between the spacer and the electrically resistive material, is carried by magnons rather than by electron movement.
39. The method of claim 16 wherein:
the electrically resistive magnet has an electrical conductance that is sufficiently negligible to ensure that a majority of heat energy, when transferred between the spacer and the electrically resistive magnet, is carried by magnons rather than by electron movement.
40. The integrated circuit of claim 6 wherein:
the electrically resistive material has sufficient electric resistance that a flux of heat carried by movement of conduction electrons constitutes none or only a minor part of an entire heat flux therethrough.
41. The integrated circuit of claim 7 wherein:
the electrically resistive material has sufficient electric resistance that a flux of heat carried by movement of conduction electrons constitutes none or only a minor part of an entire heat flux therethrough.
42. The integrated circuit of claim 1 wherein:
the electrically resistive material has sufficient electric resistance that a flux of heat carried by movement of conduction electrons constitutes none or only a minor part of an entire heat flux therethrough.
43. The method of claim 16 wherein:
the electrically resistive magnet has sufficient electric resistance that a flux of heat carried by movement of conduction electrons constitutes none or only a minor part of an entire heat flux therethrough.
44. The integrated circuit of claim 6 wherein:
the heating element is positioned such that a flow of spin current through the spacer is not coupled to the flow of heat through the spacer.
45. The integrated circuit of claim 7 wherein:
the heating element is positioned such that a flow of spin current through the spacer is not coupled to the flow of heat through the spacer.
46. The integrated circuit of claim 1 further comprising:
a heating element positioned such that a flow of spin current through the spacer is not coupled to the flow of heat through the spacer.
47. The method of claim 16 wherein:
a flow of spin current through the spacer is not coupled to the flow of heat through the spacer.
48. The integrated circuit of claim 6 wherein:
an easy axis of the electrically conductive material is at a predetermined angle that is non-zero relative to the easy axis of the electrically resistive material, so as to create a non-zero initial torque.
49. The integrated circuit of claim 7 wherein:
an easy axis of the electrically conductive material is at a predetermined angle that is non-zero relative to the easy axis of the electrically resistive material, so as to create a non-zero initial torque.
50. The integrated circuit of claim 1 wherein:
an easy axis of the electrically conductive material is at a predetermined angle that is non-zero relative to the easy axis of the electrically resistive material, so as to create a non-zero initial torque.
51. The method of claim 16 wherein:
an easy axis of the electrically conductive magnet is at a predetermined angle that is non-zero relative to the easy axis of the electrically resistive magnet, so as to create a non-zero initial torque.
52. The integrated circuit of claim 6 wherein:
an easy plane of the electrically conductive material is orthogonal relative to the easy axis of the electrically resistive material.
53. The integrated circuit of claim 7 wherein:
an easy plane of the electrically conductive material is orthogonal relative to the easy axis of the electrically resistive material.
54. The method of claim 16 wherein:
an easy plane of the electrically conductive magnet is orthogonal relative to the easy axis of the electrically resistive magnet.
55. The integrated circuit of claim 6 wherein:
the electrically conductive material, the electrically resistive material and the spacer are such that when a spin current is formed between the electrically conductive material and the electrically resistive material via the spacer, there is no net flow of electric charge through the spacer.
56. The integrated circuit of claim 7 wherein:
the electrically conductive material, the electrically resistive material and the spacer are such that when a spin current is formed between the electrically conductive material and the electrically resistive material via the spacer, there is no net flow of electric charge through the spacer.
57. The integrated circuit of claim 1 wherein:
the electrically conductive material, the electrically resistive material and the spacer are such that when a spin current is formed between the electrically conductive material and the electrically resistive material via the spacer, there is no net flow of electric charge through the spacer.
58. The method of claim 16 wherein:
when a spin current is formed between the electrically conductive magnet and the electrically resistive magnet via the spacer, there is no net flow of electric charge through the spacer.
59. The integrated circuit of claim 3 wherein:
the direct contact of the spacer is with the atomic monolayer comprised in the electrically resistive material.
60. The integrated circuit of claim 27 wherein:
the direct contact of the spacer is with the atomic monolayer comprised in the electrically resistive material.
61. The integrated circuit of claim 6 wherein:
the electrically resistive material comprises at least one of: meghamite \u03b3Fe2O3, nickel ferrite NiFe2O4, manganese-magnesium ferrite (Mn,Mg)Fe2O4, lithium-iron ferrite Li0.5 Fe2.5O4, lithium-zinc ferrite (Li,Zn,Fe)3O4, yttrium iron garnet Y3Fe5O12, yttrium-gadolimium iron garnet (Y,Gd)3Fe5O12, barium hexaferrite BaFe12O19, barium gadolinium-iron hexaferrite Ba(Gd, Fe)12O19, and aluminum-iron hexaferrite Ba(Fe, Al)12O19.
62. The integrated circuit of claim 7 wherein:
the electrically resistive material comprises at least one of: meghamite \u03b3Fe2O3, nickel ferrite NiFe2O4, manganese-magnesium ferrite (Mn,Mg)Fe2O4, lithium-iron ferrite Li0.5 Fe2.5O4, lithium-zinc ferrite (Li,Zn,Fe)3O4, yttrium iron garnet Y3Fe5O12, yttrium-gadolimium iron garnet (Y,Gd)3Fe5O12, barium hexaferrite BaFe12O19, barium gadolinium-iron hexaferrite Ba(Gd, Fe)12O19, and aluminum-iron hexaferrite Ba(Fe, Al)12O19.
63. The integrated circuit of claim 6 wherein:
transfer of heat across an interface between the electrically resistive material and the spacer changes an angle \u03b8 between spin moment vector Sfm of the electrically conductive material and spin moment vector Sfrt of the electrically resistive material.
64. The integrated circuit of claim 7 wherein:
transfer of heat across an interface between the electrically resistive material and the spacer changes an angle \u03b8 between spin moment vector Sfm of the electrically conductive material and spin moment vector Sfrt of the electrically resistive material.
65. The integrated circuit of claim 25 wherein:
transfer of heat across an interface between the electrically resistive material and the spacer changes an angle \u03b8 between spin moment vector Sfm of the electrically conductive material and spin moment vector Sfrt of the electrically resistive material.
66. The method of claim 16 wherein:
the heat is transferred at least across an interface between the electrically resistive magnet and the spacer.
67. An integrated circuit comprising:
an electrically conductive material possessing spontaneous magnetization;
an electrically resistive material possessing spontaneous magnetization;
wherein the electrically resistive material has an electrical conductance lower than the electrical conductance of the electrically conductive material, by at least multiple orders of magnitude;
wherein the electrical conductive material and the electrically resistive material do not contact each other;
a spacer comprising atomically unbound electrons to transfer spin between the electrically resistive material and the electrically conductive material;
wherein the spacer is in direct contact with the electrically resistive material; and
a heating element positioned to cause heat to flow at least across an interface between the spacer and the electrically resistive material.
68. The integrated circuit of claim 67 wherein:
the heat, when flowing across the interface, generates a spin current.
69. The integrated circuit of claim 67 further comprising:
a thermal barrier having smaller thermal conductance than the electrically resistive material.
70. The integrated circuit of claim 67 further comprising:
a heat sink located in thermal contact with the electrically resistive material.
71. The integrated circuit of claim 67 further comprising:
a heat sink located in thermal contact with the electrically conductive material.
72. The integrated circuit of claim 67 wherein:
the heating element is comprised in or in direct thermal contact with at least one of the electrically conductive material, the spacer and the electrically resistive material.
73. The integrated circuit of claim 67 wherein:
the spacer comprises a metal.
74. The integrated circuit of claim 67 wherein:
the spacer comprises a metal; and
said metal is at least one of: copper, silver and gold.
75. The integrated circuit of claim 67 wherein:
the electrically resistive material comprises at least one of: meghamite \u03b3Fe2O3, nickel ferrite NiFe2O4, manganese-magnesium ferrite (Mn,Mg)Fe2O4, lithium-iron ferrite Li0.5 Fe2.5O4, lithium-zinc ferrite (Li,Zn,Fe)3O4, yttrium iron garnet Y3Fe5O12, yttrium-gadolimium iron garnet (Y,Gd)3Fe5O12, barium hexaferrite BaFe12O19, barium gadolinium-iron hexaferrite Ba(Gd, Fe)12O19, and aluminum-iron hexaferrite Ba(Fe, Al)12O19.
76. The integrated circuit of claim 67 wherein:
the electrically resistive material comprises a cubic crystalline ferrimagnetic oxide.
77. The integrated circuit of claim 67 further comprising:
an electrode located between the electrically resistive material and a diffuse silicon resistor material.
78. The integrated circuit of claim 77 further comprising:
an additional electrode located in contact with the diffuse silicon resistor material.