1. A method for operating a semiconductor memory comprising:
isolating a connection of a sense amplifier from a bit line by an isolation transistor;
reading out a memory cell to the bit line;
waiting until a predetermined delay time has elapsed, so that a leakage current measurably changes a voltage on the bit line within the delay time;
short-circuiting the sense amplifier with the bit line by the isolation transistor;
collecting the voltage on the bit line by the sense amplifier; and
using the collected voltage to detect the leakage current.
2. The method according to claim 1, comprising:
detecting the leakage current by comparing the collected voltage to a reference voltage.
3. The method according to claim 1, comprising:
connecting the sense amplifier and the isolation transistor between the bit line to be tested and the connection of the sense amplifier.
4. The method according to claim 3, comprising:
connecting the sense amplifier and the isolation transistor so as to isolate the bit line from the sense amplifier.
5. The method according to claim 3, comprising:
connecting the sense amplifier and the isolation transistor to connect the bit line to the sense amplifier.
6. The method according to claim 1, comprising:
reading out a DRAM memory cell.
7. The method according to claim 1, comprising:
keeping the connection of the sense amplifier on a constant potential during the delay time.
8. A method for detecting a leakage current in a bit line of a semiconductor memory comprising:
connecting a sense amplifier and an isolation transistor between the bit line to be tested and a connection of the sense amplifier so as to isolate the bit line from the sense amplifier or to connect the bit line to the sense amplifier;
isolating the connection of the sense amplifier from the bit line by means of the isolation transistor;
reading out a memory cell to the bit line;
waiting until a predetermined delay time has elapsed, so that a leakage current measurably changes the voltage on the bit line within the delay time;
short-circuiting the sense amplifier with the bit line by means of the isolation transistor; and
collecting the voltage on the bit line by the sense amplifier.
9. The method according to claim 8, comprising keeping the connection of the sense amplifier on a constant potential during the delay time.
10. A method according for detecting a leakage current in a bit line of a semiconductor memory, comprising:
defining the semiconductor memory to include a first and a second bit line which are both connected to the connection of the sense amplifier, a first isolation transistor for isolating the first bit line from the connection, and a second isolation transistor for isolating the second bit line from the connection; and
short-circuiting the sense amplifier with the first bit line so as to collect the voltage on the first bit line, the sense amplifier is isolated from the second bit line by means of the second isolation transistor, and while the sense amplifier is short-circuited with the second bit line so as to collect the voltage on the second bit line, the sense amplifier is isolated from the first bit line by means of the first isolation transistor.
11. The method according to claim 10, comprising wherein the delay time for detecting the leakage current on the first bit line elapses, the connection of the sense amplifier is kept on a constant potential in that the connection is short-circuited with the precharged second bit line, while the delay time for detecting the leakage current on the second bit line elapses, the connection of the sense amplifier is kept on a constant potential in that the connection is short-circuited with the precharged first bit line.
12. A semiconductor memory comprising:
a bit line;
a sense amplifier comprising a connection;
an isolation transistor connected between the bit line to be tested and the connection of the sense amplifier so as to isolate the bit line from the sense amplifier or to connect the bit line to the sense amplifier, as required; and
a control circuit for detecting a leakage current in the bit line of the semiconductor memory, wherein the control circuit is configured to control the semiconductor memory comprising isolating the connection of the sense amplifier from the bit line by means of the isolation transistor, reading out a memory cell to the bit line, predetermining delay time elapses, so that the leakage current measurably changes the voltage on the bit line within the delay time, short-circuiting the sense amplifier with the bit line by means of the isolation transistor, and collecting the voltage on the bit line by the sense amplifier.
13. A DRAM semiconductor memory comprising:
a bit it line
a sense amplifier:
a control circuit for detecting the leakage current of the bit line, including an isolation transistor connected between the bit line and a connection of the sense amplifier, wherein the bit line is configured to be isolated from the sense amplifier via the isolation transistor, the control circuit is configured to read out reading out a DRAM memory cell to the bit line, wait until a predetermined delay time has elapsed, so that a leakage current measurably changes a voltage on the bit line within the delay time, short-circuit the sense amplifier with the bit line by the isolation transistor, collect the voltage on the bit line by the sense amplifier, and use the collected voltage to detect the leakage current.
14. The memory according to claim 13, comprising:
where the control circuit is configured to detect the leakage current by comparing the collected voltage to a reference voltage.
15. The memory according to claim 13, comprising:
where the sense amplifier and the isolation transistor are connected between the bit line to be tested and the connection of the sense amplifier.
16. The memory according to claim 13, comprising:
where the sense amplifier and the isolation transistor are connected so as to isolate the bit line from the sense amplifier.
17. The method according to claim 13, comprising:
where the sense amplifier and the isolation transistor are configured to connect the bit line to the sense amplifier.
18. The method according to claim 13, comprising:
where the control circuit is configured to keep the sense amplifier at a constant potential during the delay time.
19. A semiconductor memory comprising:
means for isolating a connection of a sense amplifier from a bit line by an isolation transistor;
means for reading out a memory cell to the bit line;
means for waiting until a predetermined delay time has elapsed, so that a leakage current measurably changes a voltage on the bit line within the delay time;
means for short-circuiting the sense amplifier with the bit line by the isolation transistor;
means for collecting the voltage on the bit line by the sense amplifier; and
means for using the collected voltage to detect the leakage current.
20. The method according to claim 19, comprising:
means for comparing the collected voltage to a reference voltage to detect the leakage voltage.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A method of identifying potentially optimal factorizations of a function, the method comprising:
receiving a function to be factored;
initializing a plurality of function unit circuits to implement the function, wherein each function unit circuit includes a plurality of function inputs and a function output;
specifying a first factorization of the function, wherein the first factorization specifies a first portion of the plurality of function inputs of each of the plurality of function unit circuits to be held at a different one of a set of constant values and a second portion of the plurality of function inputs of each of the plurality of function unit circuits to receive a set of input values;
providing the set of input values to the second portions of each the plurality of function unit circuits, thereby causing each of the plurality of function unit circuits to output a cofactor of the function;
determining for each cofactor at least one attribute;
comparing the plurality of attributes associated with the plurality of cofactors with at least one criteria; and
outputting data specifying the first factorization in response to the plurality of attributes satisfying the criteria.
2. The method of claim 1, further comprising:
specifying a second factorization of the function, wherein the second factorization specifies a third portion of the plurality of function inputs of each of the plurality of function unit circuits to be held at a different one of a set of constant values and a fourth portion of the plurality of function inputs of each of the plurality of function unit circuits to receive a set of input values, wherein the first portion is different than the third portion and the second portion is different than the fourth portion; and
repeating the steps of providing, determining, comparing, and outputting for the second factorization.
3. The method of claim 1, wherein receiving the function comprises:
receiving lookup table data representing the function; and
loading the lookup table data into at least one lookup table circuit associated with at least one function unit circuit.
4. The method of claim 1, wherein receiving the function comprises:
receiving programmable logic configuration data including a specification of an implementation of the function using a programmable logic circuit; and
configuring a programmable logic circuit in accordance with the programmable logic configuration data, thereby implementing the function as a programmable logic circuit.
5. The method of claim 1, wherein determining for each cofactor at least one attribute comprises:
determining digital signatures of the cofactors output by the plurality of the function unit circuits.
6. The method of claim 1, wherein determining for each cofactor at least one attribute comprises:
determining for each of the cofactors whether the cofactor is a constant value.
7. The method of claim 1, wherein determining for each cofactor at least one attribute comprises:
determining for each of the cofactors whether the cofactor is an inverse of another of the cofactors.
8. The method of claim 1, wherein determining for each cofactor at least one attribute comprises:
determining the locations of cofactor values equal to one.
9. The method of claim 1, further comprising:
receiving a second function to be factored;
initializing a second plurality of function unit circuits to implement the second function, wherein each function unit circuit of the second plurality includes a plurality of function inputs and a function output;
in response to the specification of the first factorization, further specifying a first portion of the plurality of function inputs of each of the second plurality of function unit circuits to be held at a different one of a set of constant values and a second portion of the plurality of function inputs of each of the second plurality of function unit circuits to receive the set of input values;
providing the set of input values to the second portions of each the second plurality of function unit circuits, thereby causing each of the second plurality of function unit circuits to output a cofactor of the second function;
determining for each cofactor of the second function at least one attribute;
comparing the plurality of attributes associated with the plurality of cofactors of the second function with at least one criteria; and
outputting data specifying the first factorization in response to the plurality of attributes of cofactors of the second function satisfying the criteria.
10. The method of claim 9, where comparing the attributes associated with the plurality of cofactors of the function and the second function comprises:
comparing the attributes of cofactors of the factorizations of the function and the second function with the at least one criteria to determine if the specified factorization of the function and the second function is potentially optimal for both functions.
11. The method of claim 1, wherein the plurality of function unit circuits output their cofactors of the function simultaneously, and the attributes of the cofactors of the plurality of function unit circuits are determined simultaneously.
12. The method of claim 1, wherein the function is received from a design compilation software application executing on a computer system.