1. A switching power supply device comprising:
a switching control circuit that generates a switching control signal such that a desired voltage is generated as an output voltage from an input voltage;
a drive circuit that turns onoff an output transistor in accordance with the switching control signal; and
an on-pulse stop circuit that generates a pulse stop signal such that a number of ON pulses of the switching control signal is reduced in a state where a load is heavier than a first threshold but is lighter than a second threshold.
2. The switching power supply device according to claim 1,
wherein the on-pulse stop circuit generates the pulse stop signal by comparing a feedback voltage in accordance with the output voltage with a threshold voltage in accordance with a time average value of the feedback voltage.
3. The switching power supply device according to claim 2,
wherein the on-pulse stop circuit generates the threshold voltage by multiplying the time average value of the feedback voltage by a coefficient that is larger than zero but smaller than one.
4. The switching power supply device according to claim 3,
wherein the coefficient is adjustable by means of an external resistor.
5. The switching power supply device according to claim 1,
wherein, in a state where the load is lighter than the first threshold, the on-pulse stop circuit puts the pulse stop signal to a logic level taken at a time of pulse suspension such that the ON pulses of the switching control signal are suspended for a plurality of cycles.
6. The switching power supply device according to claim 1,
wherein, in a state where the load is heavier than the second threshold, the on-pulse stop circuit puts the pulse stop signal to a logic level taken at a time of cancellation of pulse suspension such that the number of ON pulses of the switching control signal is not reduced.
7. The switching power supply device according to claim 1,
wherein the switching control circuit includes:
an on-signal generation portion that generates an ON signal at a predetermined switching frequency;
an off-signal generation portion that generates an OFF signal by means of output feedback control;
a flip-flop that generates the switching control signal in accordance with the ON signal and the OFF signal; and
a logic gate portion that masks the ON signal in accordance with the pulse stop signal.
8. The switching power supply device according to claim 1, further comprising
an ACDC conversion portion that generates the input voltage from an AC voltage.
9. An AC adapter comprising
the switching power supply device according to claim 8.
10. An electronic apparatus comprising:
the switching power supply device according to claim 1; and
a load operable by receiving supply of the output voltage from the switching power supply device.
11. The switching power supply device according to claim 2,
wherein, in a state where the load is lighter than the first threshold, the on-pulse stop circuit puts the pulse stop signal to a logic level taken at a time of pulse suspension such that the ON pulses of the switching control signal are suspended for a plurality of cycles.
12. The switching power supply device according to claim 3,
wherein, in a state where the load is lighter than the first threshold, the on-pulse stop circuit puts the pulse stop signal to a logic level taken at a time of pulse suspension such that the ON pulses of the switching control signal are suspended for a plurality of cycles.
13. The switching power supply device according to claim 4,
wherein, in a state where the load is lighter than the first threshold, the on-pulse stop circuit puts the pulse stop signal to a logic level taken at a time of pulse suspension such that the ON pulses of the switching control signal are suspended for a plurality of cycles.
14. The switching power supply device according to claim 2,
wherein, in a state where the load is heavier than the second threshold, the on-pulse stop circuit puts the pulse stop signal to a logic level taken at a time of cancellation of pulse suspension such that the number of ON pulses of the switching control signal is not reduced.
15. The switching power supply device according to claim 3,
wherein, in a state where the load is heavier than the second threshold, the on-pulse stop circuit puts the pulse stop signal to a logic level taken at a time of cancellation of pulse suspension such that the number of ON pulses of the switching control signal is not reduced.
16. The switching power supply device according to claim 4,
wherein, in a state where the load is heavier than the second threshold, the on-pulse stop circuit puts the pulse stop signal to a logic level taken at a time of cancellation of pulse suspension such that the number of ON pulses of the switching control signal is not reduced.
17. The switching power supply device according to claim 5,
wherein, in a state where the load is heavier than the second threshold, the on-pulse stop circuit puts the pulse stop signal to a logic level taken at a time of cancellation of pulse suspension such that the number of ON pulses of the switching control signal is not reduced.
18. The switching power supply device according to claim 2,
wherein the switching control circuit includes:
an on-signal generation portion that generates an ON signal at a predetermined switching frequency;
an off-signal generation portion that generates an OFF signal by means of output feedback control;
a flip-flop that generates the switching control signal in accordance with the ON signal and the OFF signal; and
a logic gate portion that masks the ON signal in accordance with the pulse stop signal.
19. The switching power supply device according to claim 3,
wherein the switching control circuit includes:
an on-signal generation portion that generates an ON signal at a predetermined switching frequency;
an off-signal generation portion that generates an OFF signal by means of output feedback control;
a flip-flop that generates the switching control signal in accordance with the ON signal and the OFF signal; and
a logic gate portion that masks the ON signal in accordance with the pulse stop signal.
20. The switching power supply device according to claim 4,
wherein the switching control circuit includes:
an on-signal generation portion that generates an ON signal at a predetermined switching frequency;
an off-signal generation portion that generates an OFF signal by means of output feedback control;
a flip-flop that generates the switching control signal in accordance with the ON signal and the OFF signal; and
a logic gate portion that masks the ON signal in accordance with the pulse stop signal.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A multi-core processor system comprising a plurality of cores; a memory controller including a plurality of ports corresponding to the cores; and shared memory including physical address spaces divided among the ports, wherein
a designated core among the cores is configured to:
acquire from a database storing for each software, the number of cores to which the software is to be assigned, the number of cores to which software to be executed is to be assigned;
determine cores to which the software to be executed is to be assigned, based on the acquired number of cores and a state of use of the cores;
set, for each of the determined cores, physical address spaces that correspond to logical address spaces defined by the software to be executed and are among physical address spaces accessible by a designated port that is among the ports and corresponds to the determined cores;
notify the designated port of the set physical address spaces and the logical address spaces corresponding to the set physical address spaces; and
notify the software to be executed of a start of execution after notification to the designated port has been executed.
2. The multi-core processor system according to claim 1, the designated core configured to:
select, when a plurality of designated ports are present corresponding to the determined cores, an arbitrary port from among the designated ports;
notify ports remaining after excluding the selected port from among the designated ports, of cancellation of connection of the ports remaining; and
aggregate physical address spaces accessible by the designated ports, wherein
the designated core sets the aggregated physical address spaces in physical address spaces newly accessible by the selected port, and
the designated core notifies the selected port of the newly accessible physical address spaces.
3. The multi-core processor system according to claim 2, the designated core configured to
detect, upon determining a plurality of cores, a starting time for the determined cores to simultaneously execute the software to be executed, wherein
the designated core notifies the designated ports of the set physical address spaces and the logical address spaces corresponding to the set physical address spaces,
the designated core detects, as the starting time, the time at which the notification to the designated ports is completed, and
the designated core notifies the software to be executed of the start of execution, after detecting the starting time.
4. The multi-core processor system according to claim 3, wherein
the number of cores and the number of ports are equivalent.
5. A memory controller control method of controlling a memory controller that comprises a plurality of ports and controls shared memory comprising physical address spaces divided among the ports corresponding to a plurality of cores, the method being executed by a designated core among the cores and the method comprising:
acquiring from a database storing for each software, the number of cores to which the software is to be assigned, the number of cores to which software to be executed is to be assigned;
determining cores to which the software to be executed is to be assigned, based on the acquired number of cores and a state of use of the cores;
setting, for each of the determined cores, physical address spaces that correspond to logical address spaces defined by the software to be executed and are among physical address spaces accessible by a designated port that is among the ports and corresponds to the determined cores;
notifying the designated port of the set physical address spaces and the logical address spaces corresponding to the set physical address spaces; and
notifying the software to be executed of a start of execution after notification to the designated port has been executed.
6. A computer-readable recording medium storing a program causing a designated core to execute a process of controlling a memory controller that comprises a plurality of ports and controls shared memory comprising physical address spaces divided among the ports corresponding to a plurality of cores, the designated core being among the cores and the process comprising:
acquiring from a database storing for each software, the number of cores to which the software is to be assigned, the number of cores to which software to be executed is to be assigned;
determining cores to which the software to be executed is to be assigned, based on the acquired number of cores and a state of use of the cores;
setting, for each of the determined cores, physical address spaces that correspond to logical address spaces defined by the software to be executed and are among physical address spaces accessible by a designated port that is among the ports and corresponds to the determined cores;
notifying the designated port of the set physical address spaces and the logical address spaces corresponding to the set physical address spaces; and
notifying the software to be executed of a start of execution after notification to the designated port has been executed.