1. Multiple glazing for a building window, comprising a plurality of glass sheets and a spacer is placed for the periphery edges of the plurality of glass sheets to form an air space between adjacent glass sheets, wherein among the plurality of glass sheets, a glass sheet arranged on the indoor side has first and second main surfaces and an edge present between the first and second main surfaces, and is a glass sheet having a surface compression stress formed at both of the main surfaces by chemical tempering and having a tensile stress formed inside; said glass sheet has a sheet thickness of from 1.0 to 2.5 mm; the value of said surface compression stress formed at both of the main surfaces is from 400 to 900 MPa; the value of said tensile stress is from 1 to 25 MPa; and the thickness in the sheet thickness direction of the compression stress layer at both of the main surfaces is from 7 to 25 \u03bcm.
2. The multiple glazing for a building window according to claim 1, wherein the thickness of the glass sheet arranged on the indoor side is from 1.2 to 2.2 mm; the value of said surface compression stress is from 600 to 850 MPa; the value of said tensile stress is from 4 to 20 MPa; and the thickness in the sheet thickness direction of the compression stress layer at the main surfaces is from 15 to 25 \u03bcm.
3. The multiple glazing for a building window according to claim 1, wherein when the multiple glazing for a building window is subjected to a pendulum impact test in accordance with JIS R3206 from the side of said glass sheet arranged on the indoor side, it does not break at a drop height of 10 cm, and when it breaks at a drop height of at least 20 cm, the scattering distance of a fragment exceeding 0.15 g is at most 4.5 m.
4. The multiple glazing for a building window according to claim 1, wherein the area of each main surface is at least 5,000 cm2.
5. The multiple glazing for a building window according to claim 1, wherein said glass sheet arranged on the indoor side is made of glass comprising, as represented by mol percentage based on the following oxides, from 56 to 75% of SiO2, from 1 to 20% of Al2O3, from 8 to 22% of Na2O, from 0 to 10% of K2O, from 0 to 14% of MgO, from 0 to 5% of ZrO2, and from 0 to 10% of CaO.
6. The multiple glazing for a building window according to claim 1, wherein said glass sheet arranged on the indoor side is made of glass comprising, as represented by mol percentage based on the following oxides, from 56 to 75% of SiO2, from 5 to 20% of Al2O3, from 8 to 22% of Na2O, from 0 to 10% of K2O, from 0 to 14% of MgO, from 0 to 5% of ZrO2, and from 0 to 5% of CaO.
7. The multiple glazing for a building window according to claim 1, wherein the thickness of the air space is from 6 to 16 mm.
8. Multiple glazing for a building window, comprising first, second and third glass sheets, and first and second spacers is placed for the periphery edges of the respective glass sheets to form a first air space between the first and second glass sheets, and a second air space between the second and third glass sheets, wherein the first glass sheet arranged on the indoor side has first and second main surfaces and an edge present between the first and second main surfaces, and is a glass sheet having a surface compression stress formed at both of the main surfaces by chemical tempering and having a tensile stress formed inside; said glass sheet has a sheet thickness of from 1.0 to 2.5 mm; the value of said surface compression stress formed at both of the main surfaces is from 400 to 900 MPa; the value of said tensile stress is from 1 to 25 MPa; and the thickness in the sheet thickness direction of the compression stress layer at both of the main surfaces is from 7 to 25 \u03bcm.
9. The multiple glazing for a building window according to claim 8, wherein the thickness of the first air space and the thickness of the second air space are from 6 to 16 mm.
10. The multiple glazing for a building window according to claim 9, wherein the thickness of the first air space and the thickness of the second air space are different.
11. The multiple glazing for a building window according to claims 8, wherein the sheet thickness of the glass sheet arranged on the indoor side is from 1.2 to 2.2 mm; the value of said surface compression stress is from 600 to 850 MPa; the value of said tensile stress is from 4 to 20 MPa; and the thickness in the sheet thickness direction of the compression stress layer at the main surfaces is from 15 to 25 \u03bcm.
12. The multiple glazing for a building window according to claim 8, wherein when the multiple glazing for a building window is subjected to a pendulum impact test in accordance with JIS R3206 from the side of said glass sheet arranged on the indoor side, it does not break at a drop height of 10 cm, and when it breaks at a drop height of at least 20 cm, the scattering distance of a fragment exceeding 0.15 g is at most 4.5 m.
13. The multiple glazing for a building window according to claim 8, wherein the area of each main surface is at least 5,000 cm2.
14. The multiple glazing for a building window according to claim 8, wherein the first glass sheet arranged on the indoor side is made of glass comprising, as represented by mol percentage based on the following oxides, from 56 to 75% of SiO2, from 1 to 20% of Al2O3, from 8 to 22% of Na2O, from 0 to 10% of K2O, from 0 to 14% of MgO, from 0 to 5% of ZrO2, and from 0 to 10% of CaO.
15. The multiple glazing for a building window according to claim 8, wherein the first glass sheet arranged on the indoor side is made of glass comprising, as represented by mol percentage based on the following oxides, from 56 to 75% of SiO2, from 5 to 20% of Al2O3, from 8 to 22% of Na2O, from 0 to 10% of K2O, from 0 to 14% of MgO, from 0 to 5% of ZrO2, and from 0 to 5% of CaO.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1-8. (canceled)
9. A device specific information generation device for generating specific information of a semiconductor device in the semiconductor device, comprising:
a glitch generation circuit comprising logic circuits connected in series to have a multi-stage configuration, for outputting a plurality of different glitches generated in output signals of respective stages;
a selector for receiving a selection signal from outside to select one glitch from among the plurality of different glitches output from the glitch generation circuit, and outputting the selected one glitch;
a bit conversion circuit for converting a shape of the one glitch selected by the selector into bit information; and
a performance evaluation and control unit for outputting the selection signal so that the plurality of different glitches are selected one by one to obtain respective pieces of bit information converted by the bit conversion circuit so as to correspond to the plurality of different glitches, evaluating performances of the obtained pieces of bit information to specify a glitch to be selected, and specifying the selection signal so that the specified glitch is output as the specific information of the semiconductor device.
10. The device specific information generation device according to claim 9, wherein the glitch generation circuit comprises a plurality of glitch generation circuits having different circuit configurations, and outputs respective output signals of the plurality of glitch generation circuits as the plurality of different glitches.
11. The device specific information generation device according to claim 9, wherein the performance evaluation and control unit comprises an error rate evaluation circuit for repeatedly executing an operation of outputting the selection signal so that the plurality of different glitches are selected one by one to obtain each of pieces of bit information converted by the bit conversion circuit so as to correspond to each of the plurality of different glitches, and evaluating an error rate of the each of the plurality of different glitches based on a ratio of a number of times for which the obtained pieces of bit information match one another to a repetition count.
12. The device specific information generation device according to claim 10, wherein the performance evaluation and control unit comprises an error rate evaluation circuit for repeatedly executing an operation of outputting the selection signal so that the plurality of different glitches are selected one by one to obtain each of pieces of bit information converted by the bit conversion circuit so as to correspond to each of the plurality of different glitches, and evaluating an error rate of the each of the plurality of different glitches based on a ratio of a number of times for which the obtained pieces of bit information match one another to a repetition count.
13. The device specific information generation device according to claim 9,
wherein the single semiconductor device has mounted thereon a plurality of glitch generation circuit groups each comprising a plurality of glitch generation circuits having different circuit configurations,
wherein the device specific information generation device further comprises a second selector for receiving a second selection signal from outside to select one output from among outputs of the plurality of glitch generation circuit groups, and outputting the selected one output to the bit conversion circuit, and
wherein the performance evaluation and control unit comprises an information amount evaluation circuit for executing an operation of outputting the second selection signal so that the outputs of the plurality of glitch generation circuit groups are selected one by one and changing an n-bit input signal, where n is an integer of 2 or larger, to be input to each of the plurality of glitch generation circuit groups to obtain each of pieces of bit information converted by the bit conversion circuit so as to correspond to the each of the plurality of glitch generation circuit groups as a bit sequence having 2n\u22121 bits, and evaluating an amount of information of the each of the plurality of glitch generation circuit groups by counting a number of bits that are included in the bit sequence and have a bit value of 1.
14. The device specific information generation device according to claim 10,
wherein the single semiconductor device has mounted thereon a plurality of glitch generation circuit groups each comprising a plurality of glitch generation circuits having different circuit configurations,
wherein the device specific information generation device further comprises a second selector for receiving a second selection signal from outside to select one output from among outputs of the plurality of glitch generation circuit groups, and outputting the selected one output to the bit conversion circuit, and
wherein the performance evaluation and control unit comprises an information amount evaluation circuit for executing an operation of outputting the second selection signal so that the outputs of the plurality of glitch generation circuit groups are selected one by one and changing an n-bit input signal, where n is an integer of 2 or larger, to be input to each of the plurality of glitch generation circuit groups to obtain each of pieces of bit information converted by the bit conversion circuit so as to correspond to the each of the plurality of glitch generation circuit groups as a bit sequence having 2n\u22121 bits, and evaluating an amount of information of the each of the plurality of glitch generation circuit groups by counting a number of bits that are included in the bit sequence and have a bit value of 1.
15. The device specific information generation device according to claim 11, wherein the performance evaluation and control unit comprises:
an error correction circuit for correcting an error included in a bit sequence, which is input to the performance evaluation and control unit via the bit conversion circuit;
an OWHF circuit for generating a hash value of the bit sequence that has been subjected to the error correction by the error correction circuit;
a comparisondetermination circuit for comparing the hash value generated by the OWHF circuit with a hash value generated previously;
a performance evaluation circuit for evaluating the error rate or the amount of information as a performance of the bit sequence; and
a control circuit for performing control so that the bit information converted by the bit conversion circuit is generated from a glitch satisfying a desired performance based on a result of the determination obtained by the comparisondetermination circuit and a result of the evaluation obtained by the performance evaluation circuit.
16. The device specific information generation device according to claim 12, wherein the performance evaluation and control unit comprises:
an error correction circuit for correcting an error included in a bit sequence, which is input to the performance evaluation and control unit via the bit conversion circuit;
an OWHF circuit for generating a hash value of the bit sequence that has been subjected to the error correction by the error correction circuit;
a comparisondetermination circuit for comparing the hash value generated by the OWHF circuit with a hash value generated previously;
a performance evaluation circuit for evaluating the error rate or the amount of information as a performance of the bit sequence; and
a control circuit for performing control so that the bit information converted by the bit conversion circuit is generated from a glitch satisfying a desired performance based on a result of the determination obtained by the comparisondetermination circuit and a result of the evaluation obtained by the performance evaluation circuit.
17. The device specific information generation device according to claim 13, wherein the performance evaluation and control unit comprises:
an error correction circuit for correcting an error included in a bit sequence, which is input to the performance evaluation and control unit via the bit conversion circuit;
an OWHF circuit for generating a hash value of the bit sequence that has been subjected to the error correction by the error correction circuit;
a comparisondetermination circuit for comparing the hash value generated by the OWHF circuit with a hash value generated previously;
a performance evaluation circuit for evaluating the error rate or the amount of information as a performance of the bit sequence; and
a control circuit for performing control so that the bit information converted by the bit conversion circuit is generated from a glitch satisfying a desired performance based on a result of the determination obtained by the comparisondetermination circuit and a result of the evaluation obtained by the performance evaluation circuit.
18. The device specific information generation device according to claim 14, wherein the performance evaluation and control unit comprises:
an error correction circuit for correcting an error included in a bit sequence, which is input to the performance evaluation and control unit via the bit conversion circuit;
an OWHF circuit for generating a hash value of the bit sequence that has been subjected to the error correction by the error correction circuit;
a comparisondetermination circuit for comparing the hash value generated by the OWHF circuit with a hash value generated previously;
a performance evaluation circuit for evaluating the error rate or the amount of information as a performance of the bit sequence; and
a control circuit for performing control so that the bit information converted by the bit conversion circuit is generated from a glitch satisfying a desired performance based on a result of the determination obtained by the comparisondetermination circuit and a result of the evaluation obtained by the performance evaluation circuit.
19. The device specific information generation device according to claim 15, wherein the performance evaluation and control unit further comprises an HF circuit for randomizing the bit sequence that has been subjected to the error correction by the error correction circuit to obtain a hash value, to thereby generate an encryption key.
20. The device specific information generation device according to claim 16, wherein the performance evaluation and control unit further comprises an HF circuit for randomizing the bit sequence that has been subjected to the error correction by the error correction circuit to obtain a hash value, to thereby generate an encryption key.
21. The device specific information generation device according to claim 17, wherein the performance evaluation and control unit further comprises an HF circuit for randomizing the bit sequence that has been subjected to the error correction by the error correction circuit to obtain a hash value, to thereby generate an encryption key.
22. The device specific information generation device according to claim 18, wherein the performance evaluation and control unit further comprises an HF circuit for randomizing the bit sequence that has been subjected to the error correction by the error correction circuit to obtain a hash value, to thereby generate an encryption key.
23. A device specific information generation method for generating specific information of a semiconductor device in the semiconductor device, comprising:
a glitch generation step of outputting a plurality of different glitches generated in output signals of respective stages by using a circuit having logic circuits connected in series to have a multi-stage configuration;
a glitch selection step of receiving a selection signal from outside to select one glitch from among the plurality of different glitches output in the glitch generation step;
a bit conversion step of converting a shape of the one glitch selected in the glitch selection step into bit information; and
a performance evaluation and control step of outputting the selection signal so that the plurality of different glitches are selected one by one to obtain respective pieces of bit information converted in the bit conversion step so as to correspond to the plurality of different glitches, evaluating performances of the obtained pieces of bit information to specify a glitch to be selected, and specifying the selection signal so that the specified glitch is output as the specific information of the semiconductor device.