1. A burner assembly comprising:
(a) a central flame holder having inlet means for an oxidant gas, inlet means for a primary fuel, a combustion region for combusting the oxidant gas and the primary fuel, and an outlet for discharging a primary effluent from the flame holder; and
(b) a plurality of secondary fuel injector nozzles surrounding the outlet of the central flame holder, wherein each secondary fuel injector nozzle comprises
(1) a nozzle body having an inlet face, an outlet face, and an inlet flow axis passing through the inlet and outlet faces; and
(2) one or more slots extending through the nozzle body from the inlet face to the outlet face, each slot having a slot axis and a slot center plane.
2. The burner assembly of claim 1 wherein each secondary fuel injector nozzle has two or more slots and the slot axes of at least two slots are not parallel to each other.
3. The burner assembly of claim 1 wherein each secondary fuel injector nozzle has two or more slots and at least two of the slots intersect each other.
4. The burner assembly of claim 3 wherein the nozzle body has four slots, wherein a first and a second slot intersect each other, and wherein a third and a fourth slot intersect each other.
5. The burner assembly of claim 3 wherein the nozzle body has three or more slots and a first slot is intersected by each of the other slots.
6. The burner assembly of claim 5 wherein the center plane of the first slot intersects the inlet flow axis at an included angle of between 0 and about 15 degrees.
7. The burner assembly of claim 5 wherein the center plane of any of the other slots intersects the inlet flow axis at an included angle of between 0 and about 30 degrees.
8. The burner assembly of claim 5 wherein the center planes of two adjacent other slots intersect at an included angle of between 0 and about 15 degrees.
9. The burner assembly of claim 8 wherein the two adjacent slots intersect at the inlet face of the nozzle body.
10. A combustion process comprising:
(a) providing burner assembly including:
(1) a central flame holder having inlet means for an oxidant gas, inlet means for a primary fuel, a combustion region for combusting the oxidant gas and the primary fuel, and an outlet for discharging a primary effluent from the flame holder; and
(2) a plurality of secondary fuel injector nozzles surrounding the outlet of the central flame holder, wherein each secondary fuel injector nozzle comprises
(2a) a nozzle body having an inlet face, an outlet face, and an inlet flow axis passing through the inlet and outlet faces; and
(2b) one or more slots extending through the nozzle body from the inlet face to the outlet face, each slot having a slot axis and a slot center plane;
(b) introducing the primary fuel and the oxidant gas into the central flame holder, combusting the primary fuel with a portion of the oxidant gas in the combustion region of the flame holder, and discharging a primary effluent containing combustion products and excess oxidant gas from the outlet of the flame holder; and
(c) injecting the secondary fuel through the secondary fuel injector nozzles into the primary effluent from the outlet of the flame holder and combusting the secondary fuel with excess oxidant gas.
11. The combustion process of claim 10 wherein the primary fuel and the secondary fuel are gases having different compositions.
12. The combustion process of claim 11 wherein the primary fuel is natural gas and the secondary fuel comprises hydrogen, methane, carbon monoxide, and carbon dioxide obtained from a pressure swing adsorption system.
13. The combustion process of claim 11 wherein the secondary fuel is introduced into the secondary fuel injector nozzles at a pressure of less than about 3 psig.
14. The combustion process of claim 10 wherein the primary fuel and the secondary fuel are gases having the same compositions.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A method of programming a memory array, comprising:
decreasing a difference of a voltage applied to a first select gate minus a voltage applied to a source coupled to the first select gate while the first select gate is off;
decreasing a difference of a voltage applied to a second select gate minus a voltage applied to a data line coupled to the second select gate while the second select gate is off; and
increasing a voltage of a signal applied to a selected access line that is coupled to an untargeted memory cell, not targeted for programming, in a string of memory cells coupled to the first and second select gates to a program voltage after or substantially concurrently with decreasing the difference of the voltage applied to the first select gate minus the voltage applied to the source and after or substantially concurrently with decreasing the difference of the voltage applied to the second select gate minus the voltage applied to the data line.
2. The method of claim 1, wherein a voltage difference across a diffusion junction under the first select gate becomes more negative as the difference of the voltage applied to the first select gate minus the voltage applied to the source decreases, and wherein a voltage difference across a diffusion junction under the second select gate becomes more negative as the difference of the voltage applied to the second select gate minus the voltage applied to the data line decreases.
3. The method of claim 2, wherein a reverse bias of the diffusion junction under the first select gate increases as the voltage difference across the diffusion junction under the first select gate decreases, and wherein a reverse bias of the diffusion junction under the second select gate increases as the voltage difference across the diffusion junction under the second select gate decreases.
4. The method of claim 3, wherein the string of memory cells coupled to the first and second select gates is formed over a semiconductor pillar, wherein one end of the semiconductor pillar forms a portion of the diffusion junction under the first select gate and an opposite end of the semiconductor pillar forms a portion of the diffusion junction under the second select gate.
5. The method of claim 4, wherein the semiconductor pillar floats when the first and second select gates are off.
6. The method of claim 1, wherein decreasing the difference of the voltage applied to the first select gate minus the voltage applied to the source comprises decreasing the voltage applied to the first select gate while the voltage applied to the source is substantially constant, increasing the voltage applied to the source while the voltage applied to the first select gate is substantially constant, or decreasing the voltage applied to the first select gate substantially concurrently with increasing the voltage applied to the source.
7. The method of claim 1, wherein decreasing the difference of the voltage applied to the second select gate minus the voltage applied to the data line comprises decreasing the voltage applied to the second select gate while the voltage applied to the data line is substantially constant, increasing the voltage applied to the data line while the voltage applied to the second select gate is substantially constant, or decreasing the voltage applied to the second select gate substantially concurrently with increasing the voltage applied to the data line.
8. The method of claim 1, further comprising increasing voltages of signals applied to unselected access lines coupled other memory cells in the string of memory cells coupled to the first and second select gates after or substantially concurrently with decreasing the difference of the voltage applied to the first select gate minus the voltage applied to the source and after or substantially concurrently with decreasing the difference of the voltage applied to the second select gate minus the voltage applied to the data line.
9. The method of claim 8, wherein increasing the voltages of signals applied to unselected access lines coupled the other memory cells in the string of memory cells coupled to the first and second select gates and increasing the voltage of the signal applied to the selected access line that is coupled to the untargeted memory cell in the string of memory cells coupled to the first and second select gates to the program voltage acts to boost a channel voltage of the string of memory cells coupled to the first and second select gates while the first and second select gates are off.
10. The method of claim 1, wherein decreasing the difference of the voltage applied to the first select gate minus the voltage applied to the source coupled to the first select gate while the first select is off and decreasing the difference of the voltage applied to the second select gate minus the voltage applied to the data line coupled to the second select gate while the second select is off occur substantially concurrently.
11. The method of claim 1, further comprising turning the first and second select gates off substantially concurrently before decreasing the difference of the voltage applied to the first select gate minus the voltage applied to the source coupled to the first select gate and before decreasing the difference of the voltage applied to the second select gate minus the voltage applied to the data line coupled to the second select gate.
12. A method of programming a memory array, comprising:
decreasing a voltage of a signal applied to a first select gate from a first voltage of the signal applied to the first select gate to a second voltage of the signal applied to the first select gate, wherein the first select gate is coupled between a string of memory cells and a source, and wherein the first select gate is on at the first voltage of the signal applied to the first select gate and turns off before the voltage of the signal applied to the first select gate reaches the second voltage of the signal applied to the first select gate;
decreasing a voltage of a signal applied to a second select gate from a first voltage of the signal applied to the second select gate to a second voltage of the signal applied to the second select gate, wherein the second select gate is coupled between the string of memory cells and a data line, and wherein the second select is on at the first voltage of the signal applied to the second select gate and turns off before the voltage of the signal applied to the second select gate reaches the second voltage of the signal applied to the second select gate; and
increasing a voltage of a signal applied to a selected access line that is coupled to an untargeted memory cell, not targeted for programming, in the string of memory cells to a program voltage after or substantially concurrently with decreasing the voltage of the signal applied to the first select gate from the first voltage of the signal applied to the first select gate to the second voltage of the signal applied to the first select gate and after or substantially concurrently with decreasing the voltage of the signal applied to the second select gate from the first voltage of the signal applied to the second select gate to the second voltage of the signal applied to the second select gate.
13. The method of claim 12, wherein a difference of the second voltage of the signal applied to the first select gate minus a voltage of a signal applied to the source is less than a threshold voltage of the first select gate and a difference of the second voltage of the signal applied to the second select gate minus a voltage of a signal applied to the data line is less than a threshold voltage of the second select gate.
14. The method of claim 12, wherein a voltage of a signal applied to the source is substantially constant or is increasing while decreasing the voltage of the signal applied to the first select gate from the first voltage of the signal applied to the first select gate to the second voltage of the signal applied to the first select gate.
15. The method of claim 12, wherein a voltage of a signal applied to the source is greater than the second voltage of the signal applied to the first select gate and less than the first voltage of the signal applied to the first select gate.
16. The method of claim 12, wherein a voltage of a signal applied to the data line is substantially constant or is increasing while decreasing the voltage of the signal applied to the second select gate from the first voltage of the signal applied to the second select gate to the second voltage of the signal applied to the second select gate.
17. The method of claim 12, wherein a voltage of a signal applied to the data line is greater than the second voltage of the signal applied to the second select gate and less than the first voltage of the signal applied to the second select gate.
18. The method of claim 12, wherein the string of memory cells comprises a first string of memory cells on a first semiconductor pillar, and further comprising decreasing a voltage of a signal applied to a third select gate coupled between a second string of memory cells on a second semiconductor pillar and the data line from a first voltage of the signal applied to the third select gate to a second voltage of the signal applied to the third select gate so that the voltage of the signal applied to the selected access line is increased to the program voltage after or while the voltage of the signal applied to the third select gate is decreased from the first voltage of the signal applied to the third select gate to the second voltage of the signal applied to the third select gate, wherein the second string of memory cells comprises a target memory cell, targeted for programming, coupled to the selected access line.
19. The method of claim 12, further comprising increasing voltages of signals applied to unselected selected access lines coupled to other memory cells in the string of memory cells after or substantially concurrently with decreasing the voltage of the signal applied to the first select gate from the first voltage of the signal applied to the first select gate to the second voltage of the signal applied to the first select gate and after or substantially concurrently with decreasing the voltage of the signal applied to the second select gate from the first voltage of the signal applied to the second select gate to the second voltage of the signal applied to the second select gate.
20. The method of claim 12, wherein decreasing the voltage of the signal applied to the first select gate from the first voltage of the signal applied to the first select gate to the second voltage of the signal applied to the first select gate occurs substantially concurrently with decreasing the voltage of the signal applied to the second select gate from the first voltage of the signal applied to the second select gate to the second voltage of the signal applied to the second select gate.
21. A method of programming a memory array, comprising:
increasing a voltage of a signal applied to a source from a first voltage of the signal applied to the source to a second voltage of the signal applied to the source, wherein the source is coupled to a first select gate, wherein the first select gate is on when the voltage of the signal applied to the source is at the first voltage of the signal applied to the source and the first select gate turns off before the voltage of the signal applied to the source reaches the second voltage of the signal applied to the source;
increasing a voltage of a signal applied to a data line from a first voltage of the signal applied to the data line to a second voltage of the signal applied to the data line, wherein the data line is coupled to a second select gate, wherein the second select gate is on when the voltage of the signal applied to the data line is at the first voltage of the signal applied to the data line and the second select gate turns off before the voltage of the signal applied to the data line reaches the second voltage of the signal applied to the data line; and
increasing a voltage of a signal applied to a selected access line that is coupled to an untargeted memory cell, not targeted for programming, in a string of memory cells coupled to the first and second select gates to a program voltage after or substantially concurrently with increasing the voltage of the signal applied to the source from the first voltage of the signal applied to the source to the second voltage of the signal applied to the source and after or substantially concurrently with increasing the voltage of the signal applied to the data line from the first voltage of the signal applied to the data line to the second voltage of the signal applied to the data line.
22. The method of claim 21, wherein the string of memory cells comprises a first string of memory cells on a first substantially vertical pillar, and wherein the data line is further coupled to a second string of memory cells on a second substantially vertical pillar and comprising a target memory cell, targeted for programming, further coupled to the selected access line.
23. The method of claim 21, further comprising keeping a voltage of a signal applied to the first select gate substantially constant or decreasing the voltage of the signal applied to the first select gate from a first voltage of the signal applied to the first select gate to a second voltage of the signal applied to the first select gate while increasing the voltage of the signal applied to the source from the first voltage of the signal applied to the source to the second voltage of the signal applied to the source.
24. The method of claim 21, further comprising keeping a voltage of a signal applied to the second select gate substantially constant or decreasing the voltage of the signal applied to the second select gate from a first voltage of the signal applied to the second select gate to a second voltage of the signal applied to the second select gate while increasing the voltage of the signal applied to the data line from the first voltage of the signal applied to the data line to the second voltage of the signal applied to the data line.
25. The method of claim 21, further comprising increasing voltages of signals applied to unselected selected access lines coupled to other memory cells in the string of memory cells after or substantially concurrently with increasing the voltage of the signal applied to the source from the first voltage of the signal applied to the source to the second voltage of the signal applied to the source and after or substantially concurrently with increasing the voltage of the signal applied to the data line from the first voltage of the signal applied to the data line to the second voltage of the signal applied to the data line.
26. The method of claim 21, further comprising while maintaining the voltage of the signal applied to the source at the first voltage of the signal applied to the source before increasing the voltage of the signal applied to the source from the first voltage of the signal applied to the source to the second voltage of the signal applied to the source, increasing the voltage of the signal applied to the data line to the first voltage of the signal applied to the data line before increasing the voltage of the signal applied to a data line from the first voltage of the signal applied to the data line to the second voltage of the signal applied to the data line.
27. The method of claim 21, wherein increasing the voltage of the signal applied to the data line from the first voltage of the signal applied to the data line to the second voltage of the signal applied to the data line and increasing the voltage of the signal applied to the source from the first voltage of the signal applied to the source to the second voltage of the signal applied to the source occur substantially concurrently.