1. A spread spectrum clock generating apparatus comprising:
a phase interpolator for receiving an input clock signal and a control signal, varying phase of an output clock signal in accordance with said control signal to output the resultant output clock signal; and
a control circuit for receiving and counting the input clock signal, generating said control signal, which is for varying the phase of the output clock signal and frequency-modulating the input signal, based upon result of the count, and supplying the generated control signal to said phase interpolator, wherein said control circuit, responsive to a frequency-modulation starting signal which is supplied thereto at any timing, starts output of said control signal, at a timing at which the frequency of the output clock signal is equal to the frequency of the input clock signal, and responsive to a frequency-modulation stop signal which is supplied thereto at any timing, stops output of said control signal, at a timing at which the frequency of the output clock signal is equal to the frequency of the input clock signal.
2. The apparatus according to claim 1, wherein said control circuit comprises a circuit for generating said control signal in such a manner that frequency of the output clock signal makes a round trip over a frequency range, stipulated by predetermined first and second frequencies of mutually different frequencies, in an interval that is a prescribed multiple of the period of the input clock signal, and supplying the generated control signal to said phase interpolator.
3. The apparatus according to claim 1, wherein said control circuit comprises a circuit for generating said control signal in such a manner that frequency of the output clock signal makes a round trip over a frequency range, stipulated by a second frequency higher by a prescribed amount than a predetermined first frequency and a third frequency lower by a prescribed amount than the first frequency, in an interval that is a prescribed multiple of the period of the input clock signal, and for supplying the generated control signal to said phase interpolator.
4. The apparatus according to claim 1, wherein said control signal includes an up signal which is for advancing the phase of the output clock andor a down signal which is for retarding the phase of the output clock signal.
5. The apparatus according to claim 1, wherein said control signal includes an up signal which is for advancing the phase of the output clock a prescribed amount and a down signal which is for retarding the phase of the output clock signal a prescribed amount; and
said control circuit comprises a circuit for exercising control so as to activate, a prescribed number of times, the up signal andor down signal based upon the result of the count every prescribed number of periods predetermined with regard to the input clock signal, and supply the activated signal to said phase interpolator.
6. The apparatus according to claim 1, wherein said control circuit comprises:
a frequency divider circuit for receiving the input clock signal and outputting a frequency-divided clock obtained by frequency dividing the input clock signal by a prescribed frequency dividing value;
a first counter for receiving and counting the frequency-divided clock signal output from said frequency divider circuit and, when the frequency-divided clock signal has been counted up to a first predetermined value, outputting a first output signal and resetting the count value to zero;
a second counter for receiving the first output signal from said first counter and counting the first output signal up and down between predetermined lower-limit and upper-limit count values;
an updown control circuit for receiving the frequency-divided clock signal from said frequency divider circuit and the count values of said first and second counters and outputting an up signal, which is for advancing the phase of the output clock, andor a down signal, which is for retarding the phase of the output clock signal, to said phase interpolator as said control signal, based upon the count values of said first and second counters, at a timing stipulated by the frequency-divided clock signal;
a comparator circuit for receiving the count value of said first counter and the count value of said second counter, detecting that all of these count values have attained prescribed logic levels and outputting a detection signal indicative of result of the comparison; and
an output control circuit for starting supply of the up signal andor down signal to said phase interpolator in accordance with the detection signal after input of the frequency modulation start signal, and stopping supply of the up signal andor down signal to said phase interpolator in accordance with the detection signal after input of the frequency modulation stop signal.
7. The apparatus according to claim 1, wherein said control signal includes a down signal which is for retarding the phase of the output clock signal a prescribed amount; and
said control circuit comprises a circuit for exercising control so as to activate, a prescribed number of times, the down signal based upon the count every prescribed number of periods predetermined with regard to the input clock signal, and supply the activated signal to said phase interpolator.
8. The apparatus according to claim 1, wherein said control circuit comprises:
a frequency divider circuit for receiving the input clock signal and outputting a frequency-divided clock obtained by frequency dividing the input clock signal by a prescribed frequency dividing value;
a first counter for receiving and counting the frequency-divided clock output from said frequency divider circuit and, when the frequency-divided clock signal has been counted up to a first predetermined value, outputting a first output signal and resetting the count value to zero;
a second counter for receiving the first output signal from said first counter and counting the first output signal up and down between predetermined lower-limit and upper-limit count values;
a down control circuit for receiving the frequency-divided clock signal from said frequency divider circuit and the count values of said first and second counters and outputting a down signal, which is for retarding the phase of the output clock signal, to said phase interpolator as said control signal based upon the count values of said first and second counters, at a timing stipulated by the frequency-divided clock signal;
a comparator circuit for receiving the count value of said first counter and the count value of said second counter, detecting that all of these count values have attained prescribed logic levels and outputting a detection signal indicative of result of the comparison; and
an output control circuit for starting supply of the down signal to said phase interpolator in accordance with the detection signal after input of the frequency modulation start signal, and stopping supply of the down signal to said phase interpolator in accordance with the detection signal after input of the frequency modulation stop signal.
9. The apparatus according to claim 1, wherein said control signal includes an up signal which is for advancing the phase of the output clock signal a prescribed amount; and
said control circuit comprises a circuit for exercising control so as to activate, a prescribed number of times, the up signal based upon the count every prescribed number of periods predetermined with regard to the input clock signal, and supply the activated signal to said phase interpolator.
10. The apparatus according to claim 1, wherein said control circuit includes:
a frequency divider circuit for receiving the input clock signal and outputting a frequency-divided clock obtained by frequency dividing the input clock signal by a prescribed frequency dividing value;
a first counter for receiving and counting the frequency-divided clock output from said frequency divider circuit and, when the frequency-divided clock has been counted up to a first predetermined value, outputting a first output signal and resetting the count value to zero;
a second counter for receiving the first output signal from said first counter and counting the first output signal up and down between predetermined lower-limit and upper-limit count values;
an up control circuit for receiving the frequency-divided clock signal from said frequency divider circuit and the count values of said first and second counters and outputting an up signal, which is for advancing the phase of the output clock signal, to said phase interpolator as said control signal based upon the count values of said first and second counters, at a timing stipulated by the frequency-divided clock;
a comparator circuit for receiving the count value of said first counter and the count value of said second counter, detecting that all of these count values have attained prescribed logic levels and outputting a detection signal indicative of result of the comparison; and
an output control circuit for starting supply of the up signal to said phase interpolator in accordance with the detection signal after input of the frequency modulation start signal, and stopping supply of the up signal to said phase interpolator in accordance with the detection signal after input of the frequency modulation stop signal.
11. The apparatus according to claim 1, wherein said phase interpolator comprises a circuit for retarding or advancing the phase of the output clock signal in accordance with said control signal, with a prescribed resolution serving as a unit of the period of the input clock signal.
12. A serial interface comprising the spread spectrum clock generating apparatus as set forth in claim 1.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A printing apparatus that performs printing by moving a printing element array, in which a plurality of printing elements for ejecting ink to a printing medium are arranged, comprising:
driving means for driving a plurality of groups at different timings, the plurality of groups being formed by dividing the plurality of printing elements in the printing element array, with each of the groups including a plurality of continuous printing elements,
wherein the driving means is able to execute driving, selectively for each group, in either a first half period or a second half period, the first half period and the second half period being established by dividing a period corresponding to one column of the printing elements;
first adjustment means configured to adjust a print position on the printing medium by one pixel unit for each of the groups by adding an offset to print data;
second adjustment means configured to adjust the print position by a unit smaller than one pixel, by selecting for each group either the first half period or the second half period for driving;
obtaining means configured to obtain inclination information of the print position when the printing element array performs printing; and
setting means configured to set (i) a first adjusting value for adjusting the print position by the first adjustment means and (ii) a second adjusting value for adjusting the print position by the second adjustment means based on the inclination information, where the second adjusting value corresponds to a selection, for each group, of the first half period or the second half period for driving,
wherein the driving means drives each of the groups at a timing corresponding to the print position adjusted by the first adjustment means and during the period corresponding to the second adjusting value.
2. The printing apparatus according to claim 1, wherein an image is formed by repeating a moving operation of moving the printing element array while ejecting ink, and a conveying operation of conveying the printing medium in a direction crossing the moving direction of the printing element array, and
wherein in the conveying operation, a conveying distance of the printing medium is equivalent to an integer times of the length of the printing element group.
3. A print position correction method of a printing apparatus that performs printing by moving a printing element array in which a plurality of printing elements for ejecting ink to a printing medium are arranged, comprising:
a driving step of driving each of a plurality of groups at different timings, where the plurality of groups are formed by dividing the plurality of printing elements in the printing element array, with each of the groups including a plurality of continuous printing elements,
wherein the driving in the driving step is executed, selectively for each group, in either a first half period or a second half period, the first half period and the second half period being established by dividing a period corresponding to one column of the printing elements;
a first adjustment step of adjusting a print position on the printing medium by one pixel unit for each of the groups by adding an offset to print data;
a second adjustment step of adjusting the print position by a unit smaller than one pixel, by selecting for each group either the first half period or the second half period for driving;
an obtaining step of obtaining inclination information of the print position when the printing element array performs printing; and
a setting step of setting (i) a first adjusting value for adjusting the print position in the first correction step and (ii) a second adjusting value for adjusting the print position in the second adjustment step based on the inclination information, where the second adjusting value corresponds to a selection, for each group, of the first half period or the second half period for driving,
wherein each of the groups is driven in the driving step at a timing corresponding to the print position adjusted in the first adjustment step and during the period corresponding to the second adjusting value.
4. A printing apparatus that performs printing by moving a printing element array in which a plurality of printing elements for ejecting ink to a printing medium are arranged, comprising:
a driving unit configured to drive a plurality of groups at different timings, the plurality of groups being formed by dividing the plurality of printing elements in the print element array, with each of the groups including a plurality of continuous printing elements,
wherein the driving unit is able to execute driving, selectively for each group, in either a first half period or a second half period, the first half period and the second half period being established by dividing a period corresponding to one column of the printing elements;
a first adjustment unit configured to adjust a print position on the printing medium by one pixel unit for each of the groups by adding an offset to print data;
a second adjustment unit configured to adjust the print position by a unit smaller than one pixel, by selecting for each group either the first half period or the second half period for driving;
an obtaining unit configured to obtain inclination information of the print position when the printing element array performs printing; and
a setting unit configured to set (i) a first adjusting value for adjusting the print position by the first adjustment unit and (ii) a second adjusting value for adjusting the print position by the second adjustment unit based on the inclination information, where the second adjusting value corresponds to a selection, for each group, of the first half period or the second half period for driving,
wherein the driving unit drives each of the groups at a timing corresponding to the print position adjusted by the first adjustment unit during the period corresponding to the second adjusting value.
5. The printing apparatus according to claim 4, wherein an image is formed by repeating a moving operation of moving the printing element array while ejecting ink, and a conveying operation of conveying the printing medium in a direction crossing the moving direction of the printing element array, and
wherein in the conveying operation, a conveying distance of the printing medium is equivalent to an integer times of the length of the printing element group.