What is claimed is:
1. A semiconductor device, comprising:
a semiconductor substrate having a main surface;
a conductive region formed on the main surface of said semiconductor substrate;
a first interconnection layer electrically connected to said conductive region, having relatively short line length and containing a material having relatively high electrical resistance;
a first insulator formed to surround said first interconnection layer and having relatively low dielectric constant;
a second interconnection layer formed on the main surface of said semiconductor substrate, containing a material having electrical resistance lower than the material contained in said first interconnection layer and having longer line length than said first interconnection layer; and
a second insulator formed to surround said second interconnection layer and having dielectric constant higher than said first insulator.
2. The semiconductor device according to claim 1, wherein said second interconnection layer and said first interconnection layer are formed in different layers on the main surface of said semiconductor substrate.
3. The semiconductor device according to claim 2, wherein said second interconnection layer is formed in a layer positioned above the layer in which said first interconnection layer is formed.
4. The semiconductor device according to claim 1, wherein said second insulator is positioned above and below said second interconnection layer.
5. The semiconductor device according to claim 1, wherein said first interconnection layer contains aluminum, and said second interconnection layer contains copper.
6. The semiconductor device according to claim 5, wherein said second insulator includes a silicon nitride film.
7. The semiconductor device according to claim 1, wherein said first insulator includes a silicon oxide film.
8. The semiconductor device according to claim 1, wherein cross sectional area of said second interconnection layer is larger than cross sectional area of said first interconnection layer.
9. The semiconductor device according to claim 1, wherein said first interconnection layer includes third and fourth interconnection layers, said second interconnection layer includes fifth and sixth interconnection layers, and distance between said fifth and sixth interconnection layers is larger than distance between said third and fourth interconnection layers.
10. The semiconductor device according to claim 1, wherein
said second interconnection layer has one side surface and the other side surface positioned opposite to said one side surface;
a barrier metal layer is formed on said one side surface and said the other side surface; and
total film thickness BM of said barrier metal layer is selected to satisfy the relation of
BMminWBMW1(K(K1))WW
where W represents set line width of said second interconnection layer in a direction approximately vertical to said one side surface,
BM represents total film thickness of said barrier metal layer formed on said one side surface and said the other side surface,
BMmin represents minimum necessary film thickness of said barrier metal layer, and
K represents tolerable ratio of increase in resistance of said second interconnection layer when said set line width W is reduced by W.
11. The semiconductor device according to claim 10, wherein said second interconnection layer has a bottom surface;
a bottom barrier metal layer is formed on said bottom surface; and
film thickness BMT of said bottom barrier metal layer is selected to satisfy the relation of
BMTminTBMTT1(KT(KT1))TT
where T represents set film thickness of said second interconnection layer in a direction approximately vertical to said bottom surface,
BMT represents film thickness of said bottom barrier metal layer,
BMTmin represents minimum necessary film thickness of said bottom barrier metal layer, and KT represents tolerable ratio of increase in resistance of said second interconnection layer when said set film thickness T is reduced by T.
12. The semiconductor device according to claim 6, wherein said first insulator includes a silicon oxide film.
13. The semiconductor device according to claim 8, wherein
said first interconnection layer includes third and fourth interconnection layers,
said second interconnection layer includes fifth and sixth interconnection layers, and
distance between said fifth and sixth interconnection layers is larger than distance between said third and fourth interconnection layers.
14. A method of designing a semiconductor circuit for a semiconductor device including a first interconnection layer having relatively short line length, a first insulator formed to surround said first interconnection layer, a second interconnection layer having long line length than said first interconnection layer and a second insulator formed to surround said second interconnection layer, comprising the steps of:
preparing a first interconnection structure pattern including a plurality of interconnection layers having a prescribed space between lines and containing a specific material, and an insulator formed to surround each of said plurality of interconnection layers and containing a specific material;
preparing a second interconnection structure pattern including a plurality of interconnection layers having a distance between lines approximately the same as said distance between lines and containing a specific material, and an insulator formed to surround each of said plurality of interconnection layers and containing a specific material;
calculating a first parasitic capacitance of each interconnection layer of said first interconnection structure pattern;
calculating a second parasitic capacitance of each interconnection layer of said second interconnection structure pattern;
selecting the material of said interconnection layer of said first or second interconnection structure pattern having smaller one of said first and second parasitic capacitances, as the material to be contained in said first interconnection layer; and
selecting the material of said insulator of said first or second interconnection structure pattern having smaller one of said first and second parasitic capacitances, as the material to be contained in said first insulator.
15. The method of designing a semiconductor circuit according to claim 14, further comprising the steps of:
calculating a first line resistance of each interconnection layer of said first interconnection structure pattern;
calculating a second line resistance of each interconnection layer in said second interconnection structure pattern;
calculating a first evaluation value by multiplying said first parasitic capacitance and said first line resistance, in said first interconnection structure pattern;
calculating a second evaluation value by multiplying said first parasitic capacitance and said second line resistance, in said second interconnection structure pattern;
selecting the material of said interconnection layer of said first or second interconnection structure pattern having smaller one of said first and second evaluation values, as the material to be contained in said second interconnection layer; and
selecting the material of said insulator of said first or second interconnection structure pattern having smaller one of said first and second evaluation values, as the material to be contained in said second insulator.
16. The method of designing a semiconductor circuit according to claim 14, wherein
said first and second interconnection structure patterns are one selected from the group consisting of
an interconnection structure pattern using aluminum as the material of the interconnection layer,
an interconnection structure pattern using copper as the material of the interconnection layer, and
an interconnection structure pattern using copper as the material of the interconnection layer with film thickness of the interconnection layer being determined to attain approximately the same line resistance as the interconnection layer of the interconnection structure pattern using aluminum as the material of said interconnection layer.
17. The method of designing a semiconductor circuit according to claim 14, wherein said distance between lines is approximately the same as minimum processing dimension in a photolithography step used in a process of manufacturing a semiconductor device.
18. A method of manufacturing a semiconductor device employing the method of designing a semiconductor circuit according to claim 14.
19. A semiconductor device, comprising:
an interconnection layer having one side surface and the other side surface positioned opposite to said one side surface; and
a barrier metal layer formed on said one side surface and said the other side surface; wherein
total film thickness BM of said barrier metal layer is selected to satisfy the relation of
BMminWBMW1(K(K1))WW
where W represents set line width of said interconnection layer in a direction approximately vertical to said one side surface,
BM represents total film thickness of said barrier metal layer formed on said one side surface and said the other side surface,
BMmin represents minimum necessary film thickness of said barrier metal layer, and
K represents tolerable ratio of increase in resistance of said interconnection layer when said set line width W is reduced by W.
20. The semiconductor device according to claim 19, wherein
said interconnection layer has a bottom surface;
a bottom barrier metal layer is formed on said bottom surface; and
total film thickness BMT of said bottom barrier metal layer is selected to satisfy the relation of
BMTminTBMTT1(KT(KT1))TT
where T represents set film thickness of said interconnection layer in a direction approximately vertical to said bottom surface,
BMT represents film thickness of said bottom barrier metal layer,
BMTmin represents minimum necessary film thickness of said bottom barrier metal layer, and
KT represents tolerable ratio of increase in resistance of said interconnection layer when said set film thickness T is reduced by T.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A method for identifying test agents that alter thyroid hormone metabolism or cholesterol and lipid metabolism comprising determining a test agent’s ability to modulate expression or activity of an orphan nuclear receptor CAR.
2. A composition for alteration of thyroid hormone metabolism or cholesterol and lipid metabolism, said composition comprising an agent which modulates CAR expression or activity in a pharmaceutically acceptable formulation.
3. The composition of claim 2 wherein the agent inhibits or decreases CAR expression or activity.
4. A method for altering thyroid hormone metabolism in a subject comprising administering to a subject in need thereof the composition of claim 2.
5. A method for altering cholesterol and lipid metabolism in a subject comprising administering to a subject in need thereof the composition of claim 3.
6. A method for treating obesity, hypercholesterolemia or dyslipidemia in a subject comprising administering to a subject suffering from obesity, hypercholesterolemia or dyslipidemia the composition of claim 3.
7. The method of claim 6 wherein the subject is suffering from obesity and the composition comprising the agent which inhibits or decreases CAR expression or activity is administered in combination with an anti-obesity agent.