1. An imaging apparatus, comprising:
an image sensor having a light receiving surface with a plurality of pixels and a color separation filter of a plurality of colors on a front side of each of the pixels, which receives light incident from a photographic subject via an optical system on the light receiving surface via the color separation filter and outputs as a pixel output of each of the pixels and images an image of the photographic subject;
a pixel output judging processor which judges if the pixel output of each of the pixels converted to data reaches a saturation level or not;
a pixel output compensation processor, in a case where a pixel output of a pixel on which a specific color filter is placed is judged to reach the saturation level by the pixel output judging processor, based on a pixel output of a pixel on which a color filter other than the specific color filter is placed in the vicinity of the pixel on which the specific color filter is placed, which performs a compensating operation to compensate the pixel output of the pixel on which the specific color filter is placed which reaches the saturation level;
a bit compression convertor which performs a bit compression such that pixel output data from the pixel output compensation processor, which is once converted from a first bit number to a second bit number larger than the first bit number, is converted again to the first bit number;
a histogram producer which produces a brightness histogram of the image of the photographic subject based on the pixel output of each of the pixels; and
a calculator which calculates a ratio of the number of pixels of a maximum brightness area of areas where a brightness distribution is plurally divided to the number of entire pixels from the brightness histogram produced by the histogram producer,
wherein the bit compression convertor performs the bit compression based on a bit compression characteristic set on the basis of the ratio of the number of pixels of the maximum brightness area calculated by the calculator, and in a case where the pixel output of the pixel on which the specific color filter is placed reaches the saturation level and the pixel output of the pixel on which the color filter other than the specific color filter is placed in the vicinity of the pixel on which the specific color filter is placed is close to the saturation level, the bit compression convertor performs the bit compression with a smaller compression rate for the bit compression on data based on a pixel output which is equal to or more than the saturation level, compared to a case where the pixel output of the pixel on which the specific color filter is placed reaches the saturation level and the pixel output of the pixel on which the color filter other than the specific color filter is placed in the vicinity of the pixel on which the specific color filter is placed is approximately \xbd of the saturation level.
2. The imaging apparatus according to claim 1, wherein in a case where the ratio of the number of pixels of the maximum brightness area to the number of the entire pixels calculated by the calculator is smaller than a predetermined threshold value, the bit compression convertor performs the bit compression based on a compression characteristic in which a compression rate for the bit compression of pixel output data of a high brightness side including the maximum brightness area is small, compared to a case where the ratio of the number of pixels of the maximum brightness area to the number of the entire pixels calculated by the calculator is larger than the predetermined threshold value.
3. The imaging apparatus according to claim 1, wherein the bit compression convertor performs the bit compression with a smaller compression rate for the bit compression on data based on a pixel output which is less than or equal to a predetermined output level than on data based on a pixel output which is equal to or more than the predetermined output level in the vicinity of the saturation level.
4. The imaging apparatus according to claim 1, wherein the bit compression convertor uses a compression rate for the bit compression to become an approximately same value before and after performing the bit compression on data based on a pixel output which is less than or equal to the saturation level and in a predetermined brightness.
5. The imaging apparatus according to claim 1, further comprising: an operation selector which selects and performs the compensating operation performed on the pixel output of the pixel where the specific color filter is placed by the pixel output compensation processor.
6. The imaging apparatus according to claim 1, wherein a processing unit for the apparatus is a size of 2\xd72 pixels in the horizontal and vertical directions.
7. The imaging apparatus according to claim 6, wherein in a case where there is a defective pixel in the processing unit, a pixel on which the same color filter as the defective pixel is placed in the vicinity of the defective pixel is used instead of the defective pixel.
8. An imaging method of an imaging apparatus including an image sensor having a light receiving surface with a plurality of pixels and a color separation filter of a plurality of colors on a front side of each of the pixels, which receives light incident from a photographic subject via an optical system on the light receiving surface via the color separation filter and outputs as a pixel output of each of the pixels and images an image of the photographic subject, comprising:
a pixel output judging processing step which judges if the pixel output of each of the pixels converted to data reaches a saturation level or not;
a pixel output compensation processing step, in a case where a pixel output of a pixel on which a specific color filter is placed is judged to reach the saturation level by the pixel output judging processing step, based on a pixel output of a pixel on which a color filter other than the specific color filter is placed in the vicinity of the pixel on which the specific color filter is placed, which performs a compensating operation to compensate the pixel output of the pixel on which the specific color filter is placed which reaches the saturation level;
a bit compression converting step which performs a bit compression such that pixel output data from the pixel output compensation processing step, which is once converted from a first bit number to a second bit number larger than the first bit number, is converted again to the first bit number;
a histogram producing step which produces a brightness histogram of the image of the photographic subject based on the pixel output of each of the pixels; and
a calculating step which calculates a ratio of the number of pixels of a maximum brightness area of areas where a brightness distribution is plurally divided to the number of entire pixels from the brightness histogram produced by the histogram producing step,
wherein the bit compression converting step performs the bit compression based on a bit compression characteristic set on the basis of the ratio of the number of pixels of the maximum brightness area calculated by the calculating step, and in a case where the pixel output of the pixel on which the specific color filter is placed reaches the saturation level and the pixel output of the pixel on which the color filter other than the specific color filter is placed in the vicinity of the pixel on which the specific color filter is placed is close to the saturation level, the bit compression converting step performs the bit compression with a smaller compression rate for the bit compression on data based on a pixel output which is equal to or more than the saturation level, compared to a case where the pixel output of the pixel on which the specific color filter is placed reaches the saturation level and the pixel output of the pixel on which the color filter other than the specific color filter is placed in the vicinity of the pixel on which the specific color filter is placed is approximately \xbd of the saturation level.
9. The imaging method according to claim 8, wherein in a case where the ratio of the number of pixels of the maximum brightness area to the number of the entire pixels calculated by the calculating step is smaller than a predetermined threshold value, the bit compression converting step performs the bit compression based on a compression characteristic in which a compression rate for the bit compression of pixel output data of a high brightness side including the maximum brightness area is small, compared to a case where the ratio of the number of pixels of the maximum brightness area to the number of the entire pixels calculated by the calculating step is larger than the predetermined threshold value.
10. The imaging method according to claim 8, wherein the bit compression converting step performs the bit compression with a smaller compression rate for the bit compression on data based on a pixel output which is less than or equal to a predetermined output level than on data based on a pixel output which is equal to or more than the predetermined output level in the vicinity of the saturation level.
11. The imaging method according to claim 8, wherein the bit compression converting step uses a compression rate for the bit compression to become an approximately same value before and after performing the bit compression on data based on a pixel output which is less than or equal to the saturation level and in a predetermined brightness.
12. The imaging method according to claim 8, further comprising: a display step which is capable of displaying image data produced based on the pixel output of each of the pixels as a monitoring image when monitoring before recording a shooting image, wherein in a case where the pixel output of the pixel where the specific color filter is placed reaches the saturation level when monitoring, an image in which the compensating operation of the pixel output of the pixel where the specific color filter is placed performed by the pixel output compensation processing step and the bit compression performed by the bit compression converting step are not performed and there is no tone in the maximum brightness area and whiteout occurs, an image in which a portion where the whiteout occurs is indicated, and an image in which the compensating operation of the pixel output of the pixel where the specific color filter is placed performed by the pixel output compensation processing step and the bit compression performed by the bit compression converting step are performed and there is a tone in the maximum brightness area are switched at predetermined time intervals and displayed as monitoring images in the display step.
13. The imaging method according to claim 8, wherein a processing unit for the imaging method is a size of 2\xd72 pixels in the horizontal and vertical directions.
14. The imaging method according to claim 13, wherein in a case where there is a defective pixel in the processing unit, a pixel on which the same color filter as the defective pixel is placed in the vicinity of the defective pixel is used instead of the defective pixel.
15. An imaging apparatus, comprising:
an image sensor having a light receiving surface with a plurality of pixels and a color separation filter of a plurality of colors on a front side of each of the pixels, which receives light incident from a photographic subject via an optical system on the light receiving surface via the color separation filter and outputs as a pixel output of each of the pixels and images an image of the photographic subject;
a pixel output judging processor which judges if the pixel output of each of the pixels converted to data reaches a saturation level or not;
a pixel output compensation processor, in a case where a pixel output of a pixel on which a specific color filter is placed is judged to reach the saturation level by the pixel output judging processor, based on a pixel output of a pixel on which a color filter other than the specific color filter is placed in the vicinity of the pixel on which the specific color filter is placed, which performs a compensating operation to compensate the pixel output of the pixel on which the specific color filter is placed which reaches the saturation level;
a bit compression convertor which performs a bit compression such that pixel output data from the pixel output compensation processor, which is once converted from a first bit number to a second bit number larger than the first bit number, is converted again to the first bit number;
a histogram producer which produces a brightness histogram of the image of the photographic subject based on the pixel output of each of the pixels;
a calculator which calculates a ratio of the number of pixels of a maximum brightness area of areas where a brightness distribution is plurally divided to the number of entire pixels from the brightness histogram produced by the histogram producer; and
a display device which is capable of displaying image data produced based on the pixel output of each of the pixels as a monitoring image when monitoring before recording a shooting image,
wherein the bit compression convertor performs the bit compression based on a bit compression characteristic set on the basis of the ratio of the number of pixels of the maximum brightness area calculated by the calculator, and in a case where the pixel output of the pixel where the specific color filter is placed reaches the saturation level when monitoring, an image in which the compensating operation of the pixel output of the pixel where the specific color filter is placed performed by the pixel output compensation processor and the bit compression performed by the bit compression convertor are not performed and there is no tone in the maximum brightness area and whiteout occurs, an image in which a portion where the whiteout occurs is indicated, and an image in which the compensating operation of the pixel output of the pixel where the specific color filter is placed performed by the pixel output compensation processor and the bit compression performed by the bit compression convertor are performed and there is a tone in the maximum brightness area are switched at predetermined time intervals and displayed as monitoring images on the display device.
16. The imaging apparatus according to claim 15, wherein in a case where the ratio of the number of pixels of the maximum brightness area to the number of the entire pixels calculated by the calculator is smaller than a predetermined threshold value, the bit compression convertor performs the bit compression based on a compression characteristic in which a compression rate for the bit compression of pixel output data of a high brightness side including the maximum brightness area is small, compared to a case where the ratio of the number of pixels of the maximum brightness area to the number of the entire pixels calculated by the calculator is larger than the predetermined threshold value.
17. The imaging apparatus according to claim 15, wherein the bit compression convertor performs the bit compression with a smaller compression rate for the bit compression on data based on a pixel output which is less than or equal to a predetermined output level than on data based on a pixel output which is equal to or more than the predetermined output level in the vicinity of the saturation level.
18. The imaging apparatus according to claim 15, wherein the bit compression convertor uses a compression rate for the bit compression to become an approximately same value before and after performing the bit compression on data based on a pixel output which is less than or equal to the saturation level and in a predetermined brightness.
19. The imaging apparatus according to claim 15, wherein a processing unit for the imaging apparatus is a size of 2\xd72 pixels in the horizontal and vertical directions.
20. The imaging apparatus according to claim 19, wherein in a case where there is a defective pixel in the processing unit, a pixel on which the same color filter as the defective pixel is placed in the vicinity of the defective pixel is used instead of the defective pixel.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. An array processor comprising:
a physical M\xd7N array organization of at least two processing elements (PEs) and a sequence processor (SP), each of the at least two PEs having a set of PE register files and the SP having a set of SP register files, the SP and at least one PE combined to form a combined processor, the combined processor having substantially similar access to the set of SP register files and to the set of PE register files of the at least one PE that was combined to form the combined processor; and
a processor state register storing a context switch bit (CSB), the CSB having a first state and a second state, the SP and each PE operating to detect the state of the CSB,
the combined processor upon detection of the first state of the CSB operating in a first operating context stored in the set SP register files, the first operating context adapted for processing a first software task where the first software task is written for an M\xd7N operating configuration which matches the physical M\xd7N array organization including the at least one PE of the combined processor, where M represents the number of rows of PEs and N represents the number of columns of PEs,
the combined processor upon detection of the second state of the CSB operating in a second operating context stored in the set of PE register files of the combined processor, the second operating context adapted for a second software task where the second software task is written for an O\xd7P operating configuration of the physical M\xd7N array organization where O is the number of rows of PEs and P is the number of columns of PEs, the O\xd7P operating configuration not matching the physical M\xd7N array organization as O+P<M+N.
2. The array processor of claim 1 further comprising:
an eventpoint mechanism to trigger a context switch from the O\xd7P operating configuration to the M\xd7N operating configuration by storing the data contents of the set of PE register files of the combined processor and the PEs in the background while the first software task uses the set of SP register files in the foreground, whereby the O\xd7P operating configuration is saved.
3. The array processor of claim 1 further comprising:
an eventpoint mechanism to trigger a context switch from the M\xd7N operating configuration to the O\xd7P operating configuration by loading the set of PE register files of the combined processor and the PEs in the background with the data contents associated with the O\xd7P operating configuration and after all of the data contents have-been loaded, the combined processor switches to the second software task.
4. The array processor of claim 1 wherein each processing element of the at least two processing elements has a physical identifier and a virtual identifier, wherein during the processing of the first software task, instructions are operable in each processing element according to its physical identifier, wherein during the processing of the second software task, instructions are operable in each processing element according to its virtual identifier taking into account the at least one FE that was combined to form the combined processor.
5. A method for providing reconfiguration of a first array processor having a physical M\xd7N array organization to emulate operation of a second array processor having a physical O\xd7P array organization where M and O represent the number of rows of processing elements (PEs) and N and P represent the number of columns of PEs, the method comprising:
providing the first array processor having at least two PEs arranged in the physical M\xd7N array organization and having a sequence processor (SP), each of the at least two PEs having a set of FE register files and the SP having a set SP register files;
combining the SP and at least one PE to form a combined processor, the combined processor having substantially similar access to the set of SP register files and to the set of PE register files of the at least one PE that was combined to form the combined processor;
storing a context switch bit (CSB), the CSB having a first state and a second state;
detecting the state of the CSB;
upon detection of the first state, operating in a first operating context stored in the set of SP register files, the first operating context adapted for processing a first software task, wherein the first software task is written for an M\xd7N operating configuration which matches the physical M\xd7N array organization including the at least one PE of the combined processor; and
upon detection of the second state, operating in a second operating context stored in the set of PE register files of the combined processor, the second operating context adapted for processing a second software task, wherein the second software task is written for an O\xd7P operating configuration on an O\xd7P subset of the physical M\xd7N array organization, where either M\u2260O or N\u2260P.
6. The method of claim 5 wherein the operating in the second operating context step further comprises:
setting the CSB to the first state; and
returning the processing to the first operating context.
7. The method of claim 5 wherein the physical M\xd7N array organization comprises a 1\xd71 layout and the emulated physical O\xd7P array organization comprises a 1\xd70 layout, wherein the 1\xd70 layout defines the sequence processor (SP) executing sequential instructions.
8. The method of claim 5 wherein the physical M\xd7N array organization comprises a 1\xd72 layout and the emulated physical O\xd7P array organization comprises a 1\xd71 layout.
9. The method of claim 5 wherein the physical M\xd7N array organization comprises a 1\xd75 layout and the emulated physical O\xd7P array organization comprises a 2\xd72 layout.
10. An apparatus for providing efficient sharing of programming resources in a merged very long instruction word (VLIW) sequence processor (SP) and VLIW processor element (PE) processor, the merged VLIW SPPE processor operating to configure an array processor to operate in an M\xd7N operating configuration or in an O\xd7P operating configuration, where M and O are the number of rows of processing elements and N and P are the number of columns of processing elements, and where O+P<M+N, the apparatus comprising:
an SP resource file having a first set of registers;
a PE resource file having a second set of registers;
an input for receiving a VLIW presented for execution, the VLIW having at least two instructions, each instruction encoded with a different setting of an SPPE-bit, wherein the state of the SPPE-bit determines whether an instruction is an SP instruction or a PE instruction; and
a processor state register storing a context switch bit (CSB), the merged VLIW SPPE processor reading the values of the CSB and the SPPE-bit of each instruction, the value of the CSB selecting the M\xd7N operating configuration or the O\xd7P operating configuration when processing each instruction, the M\xd7N operating configuration adapted for accessing at least one register from the first set of registers when processing an SP instruction as one of the at least two instructions and for accessing at least one register from the second set of registers when processing a PE instruction as the other instruction of the at least two instructions based on the value of the SPPE-bit.
11. The apparatus of claim 10 wherein the O\xd7P operating configuration is adapted for accessing at least one register from the second set of registers when processing an SP instruction and accessing at least one register from the second set of registers when processing a PE instruction based on the value of the SPPE-bit.
12. The apparatus of claim 10 wherein the SP resource file is an SP register file, an SP address register file, or an SP machine state register file.
13. The apparatus of claim 10 wherein the PE resource file is a PE register file, PE address register file, or a PE machine state register file.
14. The apparatus of claim 10 further comprising:
at least two execution units associated with the at least two instructions in the VLIW; and
a plurality of multiplexers connected to the SP and PE resource files for selecting resource files from which the at least two execution units read data and to which the at least two execution units write data, a portion of the plurality of multiplexers associated with an execution unit controlled by a logical combination of the SPPE bit and the CSB.
15. The apparatus of claim 10 wherein the VLIW SP processor and VLIW PE processor are indirect VLIW processors.