1. An electromagnetic drive for a valve, the electromagnetic drive comprising:
a housing; and
at least one electromagnetic circuit comprising:
a coil wound onto a coil carrier,
a valve closing member,
an armature movably supported between a first end position and a second end position, the armature being configured so as to act at least indirectly on the valve closing member,
a device configured to fix the armature in a currentless state,
at least one core, the at least one core being disposed at an end of the electromagnetic drive directed toward the valve closing member,
at least one magnetizable reflux device having an adjusting bore and a circumferential recess in an area of the adjusting bore on a side facing the coil, and
at least one adjustment device having an adjusting screw, the at least one adjustment device being configured to adjust a magnetic force, and the adjusting screw being configured to influence a course of magnetic field lines and to be insertable into the adjusting bore in a direction of the armature,
wherein supplying the coil with an electric current causes the armature to move into the first end position or into the second end position.
2. The electromagnetic drive as recited in claim 1, wherein the circumferential recess is provided as a groove with a penetration depth which increases in a substantially linear manner at least on a side facing the armature.
3. The electromagnetic drive as recited in claim 1, wherein the at least one magnetizable reflux device comprises a slide bearing bushing configured to support the armature.
4. The electromagnetic drive as recited in claim 1, further comprising a thread or a knurl, wherein the adjusting screw is arranged in the adjusting bore via the thread or the knurl.
5. The electromagnetic drive as recited in claim 1, wherein at least one of the at least one magnetizable reflux device and the adjusting screw comprise a respective pressure compensation bore.
6. The electromagnetic drive as recited in claim 1, further comprising a membrane comprising a radially outward face arranged in the housing and a radially inward face arranged on the valve closing member so as to seal the electromagnetic drive against the valve.
7. The electromagnetic drive as recited in claim 6, wherein the membrane includes a resilient force configured to fix the armature in the first end position.
8. The electromagnetic drive as recited in claim 1, wherein the adjusting bore of the at least one magnetizable reflux device extends to the first end position and is configured so as to receive a headless screw as the adjusting screw.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A resistance variable memory element comprising:
a plurality of layers configured to maintain a resistance state set by a programming voltage applied across said plurality of layers, said plurality of layers comprising:
at least one chalcogenide glass layer,
at least one metal-containing layer,
at least one silver layer provided adjacent to said metal-containing layer, and
at least one other glass layer,
said at least one metal-containing layer and said at least one silver layer being provided between said at least one chalcogenide glass layer and said at least one other glass layer.
2. The memory element of claim 1 wherein said at least one chalcogenide glass layer comprises a plurality of chalcogenide glass layers.
3. The memory element of claim 1 wherein said at least one other glass layer comprises a plurality of glass layers.
4. The memory element of claim 1 wherein said at least one metal-containing layer comprises a silver-chalcogenide.
5. The memory element of claim 1 wherein said at least one metal-containing layer comprises silver-selenide.
6. The memory element of claim 1 wherein said at least one metal-containing layer comprises silver-sulfide.
7. The memory element of claim 1 wherein said at least one metal-containing layer comprises silver-oxide.
8. The memory element of claim 1 wherein said at least one metal-containing layer comprises silver-telluride.
9. The memory element of claim 4 wherein said at least one chalcogenide glass layer comprises a material having a stoichiometric formula of GexSe100\u2212x, wherein 20\u03b1\xd7\u03b143.
10. The memory element of claim 9 wherein said material has the formula of about Ge40Se60.
11. The memory element of claim 4 wherein said at least one other glass layer comprises a second chalcogenide glass layer.
12. The memory element of claim 4 wherein said at least one other glass layer comprises an SiSe composition.
13. The memory element of claim 4 wherein said at least one other glass layer comprises an AsSe composition.
14. The memory element of claim 4 wherein said at least one other glass layer comprises a GeS composition.
15. The memory element of claim 4 wherein said at least one other glass layer comprises a combination of germanium, silver, and selenium.
16. The memory element of claim 1 wherein said at least one other glass layer has a thickness between about 100 \u212b and about 1000 \u212b.
17. The memory element of claim 1 wherein said at least one other glass layer has a thickness of about 150 \u212b.
18. The memory element of claim 1 wherein said at least one chalcogenide glass layer has a thickness between about 100 \u212b and about 1000 \u212b.
19. The memory element of claim 1 wherein said at least one chalcogenide glass layer has a thickness of about 150 \u212b.
20. The memory element of claim 1 wherein said at least one metal-containing layer has a first thickness and said at least one chalcogenide glass layer has a second thickness whereby a thickness ratio of said first thickness to said second thickness is between about 5:1 to about 1:1.
21. The memory element of claim 1 wherein said at least one metal-containing layer has a first thickness and said at least one chalcogenide glass layer has a second thickness whereby a thickness ratio of said first thickness to said second thickness is between about 3.3:1 to about 2:1.
22. The memory element of claim 1 wherein said at least one metal-containing layer comprises a plurality of stacked metal-containing layers.
23. The memory element of claim 1 wherein said at least one other glass layer comprises at least one second chalcogenide glass layer.
24. The memory element of claim 23 further comprising at least one second metal-containing layer in contact with said at least one second chalcogenide glass layer, a second silver layer in contact with said second metal-containing layer, and at least one third chalcogenide glass layer in contact with said second silver layer.
25. The memory element of claim 1 wherein one or more of said at least one chalcogenide glass layers contains a metal dopant.
26. The memory element of claim 25 wherein said metal dopant comprises silver.
27. The memory element of claim 1 wherein said at least one metal-containing layer has a first thickness and said at least one other glass layer has a second thickness whereby a thickness ratio of said first thickness to said second thickness is between about 5:1 to about 1:1.
28. The memory element of claim 1 wherein said at least one metal-containing layer has a first thickness and said at least one other glass layer has a second thickness whereby a thickness ratio of said first thickness to said second thickness is between about 3.3:1 to about 2:1.
29. The memory element of claim 1 wherein said at least one metal-containing layer has a thickness equal to or greater than a thickness of each of said at least one chalcogenide glass layer and said at least one other glass layer.
30. The memory element of claim 1 wherein said silver layer is an evaporated silver layer.
31. The memory element of claim 1 wherein said silver layer has a thickness of from about 50 \u212b to about 250 \u212b.
32. The memory element of claim 1 further comprising a second silver layer located on a side of said metal-containing layer opposite the side on which said at least one silver layer is located.
33. A resistance variable memory element comprising:
a first glass layer in contact with at least one silver-chalcogenide layer, and at least one silver layer in contact with said silver-chalcogenide layer, said silver layer being in contact with a second glass layer, wherein at least one of said first and second glass layers is formed of a chalcogenide glass material; and
a first electrode and a second electrode in respective contact with said first and second glass layers.
34. The memory element of claim 33 wherein said at least one silver-chalcogenide layer comprises silver-selenide.
35. The memory element of claim 33 wherein said at least one silver-chalcogenide layer comprises silver-sulfide.
36. The memory element of claim 33 wherein said at least one silver-chalcogenide layer comprises silver-oxide.
37. The memory element of claim 33 wherein said at least one silver-chalcogenide layer comprises silver-telluride.
38. The memory element of claim 33 wherein said chalcogenide glass material has a stoichiometric formula of GexSe100\u2212x, wherein 20\u03b1\xd7\u03b143.
39. The memory element of claim 33 wherein said material has the formula of about Ge40Se60.
40. The memory element of claim 33 wherein both said first glass layer and said second glass layer comprise a chalcogenide glass material.
41. The memory element of claim 33 wherein at least one of said first and second glass layers contains a metal dopant.
42. The memory element of claim 41 wherein said metal dopant comprises silver.
43. The memory element of claim 33 wherein at least another of said first and second glass layers comprises an SiSe composition.
44. The memory element of claim 33 wherein at least another of said first and second glass layers comprises an AsSe composition.
45. The memory element of claim 33 wherein at least another of said first and second glass layers comprises a GeS composition.
46. The memory element of claim 33 wherein at least another of said first and second glass layers comprises a combination of germanium, silver, and selenium.
47. The memory element of claim 33 wherein said silver-chalcogenide layer has a first thickness, said second glass layer has a second thickness, and a thickness ratio of said first thickness to said second thickness is between about 5:1 to about 1:1.
48. The memory element of claim 33 wherein said silver-chalcogenide layer has a first thickness, said second glass layer has a second thickness, and a thickness ratio of said first thickness to said second thickness is between about 3.3:1 to about 2:1.
49. The memory element of claim 33 wherein said silver-chalcogenide layer has a first thickness and said first glass layer has a second thickness and a thickness ratio of said first thickness to said second thickness is between about 5:1 to about 1:1.
50. The memory element of claim 33 wherein said silver-chalcogenide layer has a first thickness, said first glass layer has a second thickness, and a thickness ratio of said first thickness to said second thickness is between about 3.3:1 to about 2:1.
51. The memory element of claim 33 wherein said silver-chalcogenide layer has a thickness greater than or equal to the thickness of each of said first and second glass layers.
52. The memory element of claim 33 wherein said silver layer is an evaporated silver layer.
53. The memory element of claim 33 wherein said silver layer has a thickness of from about 50 \u212b to about 250 \u212b.
54. The memory element of claim 33 further comprising a second silver layer located on a side of said metal-containing layer opposite the side on which said at least one silver layer is located.
55. A memory element comprising:
a first electrode;
a first glass layer comprising GexSe100\u2212x, wherein 20\u03b1\xd7\u03b143, said first glass layer being in contact with said first electrode;
a first metal-containing layer in contact with said first glass layer;
a first silver layer in contact with said first metal-containing layer;
a second glass layer in contact with said first silver layer; and
a second electrode in contact with said second glass layer.
56. The memory element of claim 55 wherein x is about 40.
57. The memory element of claim 55 wherein said first metal-containing layer comprises a silver-chalcogenide.
58. The memory element of claim 55 wherein said first metal-containing layer comprises silver-selenide.
59. The memory element of claim 55 wherein said first metal-containing layer comprises silver-sulfide.
60. The memory element of claim 55 wherein said first metal-containing layer comprises silver-oxide.
61. The memory element of claim 55 wherein said first metal-containing layer comprises silver-telluride.
62. The memory element of claim 55 wherein said second glass layer acts as a diffusion control layer to control diffusion of components from said second electrode through said silver layer, said metal-containing layer, and said first glass layer.
63. The memory element of claim 55 wherein said second glass layer comprises an SiSe composition.
64. The memory element of claim 55 wherein said second glass layer comprises an AsSe composition.
65. The memory element of claim 55 wherein said second glass layer comprises a GeS composition.
66. The memory element of claim 55 wherein said second glass layer comprises a combination of germanium, silver, and selenium.
67. The memory element of claim 55 wherein said first metal-containing layer comprises a plurality of metal-containing layers in serial contact with each other.
68. The memory element of claim 55 wherein at least one of said first glass layer and said second glass layer comprises a plurality of glass layers in serial contact with each other.
69. The memory element of claim 55 wherein at least one of said first and second glass layers contains a metal dopant.
70. The memory element of claim 69 wherein said metal dopant comprises silver.
71. The memory element of claim 55 wherein said first silver layer is an evaporated silver layer.
72. The memory element of claim 55 wherein said first silver layer has a thickness of from about 50 \u212b to about 250 \u212b.
73. The memory element of claim 55 further comprising a second silver layer located on a side of said metal-containing layer opposite the side on which said first silver layer is located.
74. A chalcogenide glass stack comprising:
a chalcogenide glass layer;
at least one metal-containing layer in contact with said chalcogenide glass layer;
at least one silver layer in contact with said metal-containing layer; and
a diffusion control layer in contact with said silver layer for controlling diffusion of elements into said chalcogenide glass layer.
75. The chalcogenide glass stack of claim 74 wherein said diffusion control layer is a second glass layer.
76. The chalcogenide glass stack of claim 74 further comprising a metal-containing electrode in contact with said diffusion control layer and wherein said diffusion control layer slows migration of a metal from said electrode into said chalcogenide glass layer.
77. The chalcogenide glass stack of claim 74 wherein said at least one metal-containing layer comprises a silver-chalcogenide.
78. The chalcogenide glass stack of claim 74 wherein said at least one metal-containing layer comprises silver-selenide.
79. The chalcogenide glass stack of claim 74 wherein said at least one metal-containing layer comprises silver-sulfide.
80. The chalcogenide glass stack of claim 74 wherein said at least one metal-containing layer comprises silver-oxide.
81. The chalcogenide glass stack of claim 74 wherein said at least one metal-containing layer comprises silver-telluride.
82. The chalcogenide glass stack of claim 74 wherein at least one or both of said chalcogenide glass layer and said diffusion control layer contains a metal dopant.
83. The chalcogenide glass stack of claim 82 wherein said metal dopant comprises silver.
84. The chalcogenide glass stack of claim 74 wherein said silver layer is an evaporated silver layer.
85. The chalcogenide glass stack of claim 74 wherein said silver layer has a thickness of from about 50 \u212b to about 250 \u212b.
86. The chalcogenide glass stack of claim 74 further comprising a second silver layer located on a side of said metal-containing layer opposite the side on which said at least one silver layer is located.
87. A memory element comprising:
a first electrode;
at least one first chalcogenide glass layer in contact with said first electrode;
at least one first metal-containing layer in contact with said at least one first chalcogenide glass layer;
a first silver layer in contact with at said least one first metal-containing layer;
at least one second chalcogenide glass layer in contact with said first silver layer;
at least one second metal-containing layer in contact with said at least one second chalcogenide glass layer;
a second silver layer in contact with at said least one second metal-containing layer;
at least one third chalcogenide glass layer in contact with said second silver layer; and
a second electrode in contact with said at least one third chalcogenide glass layer.
88. The memory element of claim 87 wherein said metal-containing layers comprise one or more silver-selenide layers.
89. The memory element of claim 87 wherein one or more of said chalcogenide glass layers comprise a plurality of chalcogenide glass layers.
90. The memory element of claim 87 wherein one or more of said metal-containing layers comprises a plurality of metal-containing layers.
91. The memory element of claim 87 wherein one or more of said chalcogenide glass layers contains a metal dopant.
92. The memory element of claim 91 wherein said metal dopant comprises silver.
93. The memory element of claim 87 wherein each of said first and second silver layers is an evaporated silver layer.
94. The memory element of claim 87 wherein said first silver layer has a thickness of from about 50 \u212b to about 250 \u212b.
95. The memory element of claim 87 further comprising a third silver layer located on a side of said first metal-containing layer opposite the side on which said first silver layer is located, and a fourth silver layer located on a side of said second metal-containing layer opposite the side on which said second silver layer is located.
96. A method of forming a resistance variable memory element comprising the steps of:
forming a first electrode;
forming a first chalcogenide glass layer in contact with said first electrode;
forming a first metal-containing layer in contact with said first chalcogenide glass layer;
forming a first silver layer in contact with said first metal-containing layer;
forming a second chalcogenide glass layer in contact with said first silver layer;
forming a second metal-containing layer in contact with said second chalcogenide glass layer;
forming a second silver layer in contact with said second metal-containing layer;
forming a third chalcogenide glass layer in contact with said second silver layer; and
forming a second electrode in contact with said third chalcogenide glass layer.
97. The method of claim 96 wherein said chalcogenide glass layers comprise a material having the stoichiometric formula GexSe100\u2212x, wherein 20\u03b1\xd7\u03b143.
98. The method of claim 96 wherein said chalcogenide glass layers have a stoichiometry of about Ge40Se60.
99. The method of claim 96 wherein said chalcogenide glass layers comprise a plurality of chalcogenide glass layers.
100. The method of claim 96 wherein said metal-containing layers comprise a plurality of metal-containing layers.
101. The method of claim 96 wherein one or more of said chalcogenide glass layers contain a metal dopant.
102. The method of claim 96 wherein one or more of said metal-containing layers comprises silver-selenide.
103. The method of claim 101 wherein said metal dopant comprises silver.
104. The method of claim 96 wherein said metal-containing layers have a thickness which is equal to or greater than the thickness of each of said chalcogenide glass layers.
105. The method of claim 96 wherein each of said metal-containing layers has a first thickness and each of said chalcogenide glass layers has a second thickness whereby a thickness ratio of said first thickness to said second thickness is between about 5:1 to about 1:1.
106. The method of claim 105 wherein said thickness ratio of said first thickness to said second thickness is between about 3.3:1 to about 2:1.
107. The method of claim 96 wherein each of said first and second silver layers is an evaporated silver layer.
108. The method of claim 96 wherein each of said first and second silver layers has a thickness of from about so 50 \u212b to about 250 \u212b.
109. The method of claim 96 further comprising a third silver layer located on a side of said first metal-containing layer opposite the side on which said first silver layer is located, and a fourth silver layer located on a side of said second metal-containing layer opposite the side on which said second silver layer is located.
110. A method of forming a resistance variable memory element comprising a plurality of layers configured for retaining stored data as a resistance value and for exhibiting a resistance change in response to an applied programming voltage, said method comprising:
forming a first glass layer;
forming a silver-selenide layer in contact with said first glass layer;
forming at least one silver layer in contact with said silver-selenide layer; and
forming a second glass layer in contact with said silver layer, whereby one of said first and second glass layers is a formed of a chalcogenide glass material.
111. The method of claim 110 wherein said chalcogenide glass material has a stoichiometric composition of about Ge40Se60.
112. The method of claim 110 wherein at least one of said glass layers contains a metal dopant.
113. The method of claim 112 wherein said metal dopant comprises silver.
114. The method of claim 110 wherein both of said first and second glass layers comprises a chalcogenide glass material.
115. The method of claim 110 further comprising the step of forming alternating layers of said chalcogenide glass material, said silver-selenide layer, and said silver layer.
116. The method of claim 110 wherein said first or said second glass layer formed of said chalcogenide glass material further contains a metal dopant.
117. The method of claim 116 wherein said metal dopant comprises silver.
118. The method of claim 110 wherein another of said first and second glass layers controls diffusion of a metal ion from an electrode through said memory element.
119. The method of claim 118 wherein said other glass layer comprises an SiSe composition.
120. The method of claim 118 wherein said other glass layer comprises an AsSe composition.
121. The method of claim 118 wherein said other glass layer comprises a GeS composition.
122. The method of claim 118 wherein said other glass layer comprises a combination of germanium, silver, and selenium.
123. The method of claim 92 wherein said metal-containing layer has a thickness which is equal to or greater than a thickness of each of said first and second glass layers.
124. The method of claim 110 wherein said metal-containing layer comprises a plurality of silver-selenide layers in serial contact with each other.
125. The method of claim 110 wherein said silver layer is an evaporated silver layer.
126. The method of claim 110 wherein said silver layer has a thickness of from about 50 \u212b to about 250 \u212b.
127. The method of claim 110 further comprising a second silver layer located on a side of said silver-selenide layer opposite the side on which said at least one silver layer is located.
128. A processor-based system, comprising:
a processor; and
a memory circuit connected to said processor, said memory circuit including a resistance variable memory element comprising a plurality of layers configured to maintain a resistance state set by a programming voltage across said plurality of layers, said plurality of layers comprising at least one metal-containing layer, at least one silver layer in contact with said at least one metal-containing layer, at least one chalcogenide glass layer, at least one other glass layer, said metal-containing layer and said silver layer being provided between said at least one chalcogenide glass layer and said at least one other glass layer.
129. The system of claim 128 wherein said chalcogenide glass layer comprises a material having the formula GexSe100\u2212x, wherein 20\u03b1\xd7\u03b143.
130. The system of claim 129 wherein said chalcogenide glass layer stoichiometry is about Ge40Se60.
131. The system of claim 128 wherein at least one of said glass layers contains a metal dopant.
132. The system of claim 131 wherein said metal dopant comprises silver.
133. The system of claim 128 wherein said other glass layer comprises a second chalcogenide glass layer.
134. The system of claim 128 further comprising a second metal-containing layer in contact with said at least one second chalcogenide glass layer, a second silver layer in contact with said second metal-containing layer, and at least one third chalcogenide glass layer in contact with said second silver layer.
135. The system of claim 128 wherein said chalcogenide glass layer comprises a plurality of stacked chalcogenide glass layers.
136. The system of claim 128 wherein said metal-containing layer comprises a plurality of stacked metal-containing layers.
137. The system of claim 128 wherein at least one of said chalcogenide glass layers comprises a metal dopant.
138. The system of claim 128 wherein said metal-containing layer comprises silver-selenide layer.
139. The system of claim 128 wherein said other glass layer comprises an SiSe composition.
140. The system of claim 128 wherein said other glass layer comprises an AsSe composition.
141. The system of claim 128 wherein said other glass layer comprises a GeS composition.
142. The system of claim 128 wherein said other glass layer comprises a combination of germanium, silver, and selenium.
143. The system of claim 128 wherein said other glass layer is a diffusion control layer for slowing migration of a metal ion from an electrode connected thereto.
144. The system of claim 128 wherein at least one of said silver layers is an evaporated silver layer.
145. The system of claim 128 wherein each of said first and second silver layers has a thickness of from about 50 \u212b to about 250 \u212b.
146. A processor-based system, comprising:
a processor;
a memory circuit connected to said processor, said memory circuit including a first electrode;
at least one first chalcogenide glass layer in contact with said first electrode;
at least one first metal-containing layer in contact with said at least one first chalcogenide glass layer;
at least one first silver layer in contact with said at least one first metal-containing layer;
at least one second chalcogenide glass layer in contact with said at least one first silver layer;
at least one second metal-containing layer in contact with said at least one second chalcogenide glass layer;
at least one second silver layer in contact with said at least one second metal-containing layer;
at least one third chalcogenide glass layer in contact with said at least one second silver layer; and
a second electrode in contact with said at least one third chalcogenide glass layer.
147. The system of claim 146 wherein said metal-containing layers comprise one or more silver-selenide layers.
148. The system of claim 146 wherein one or more of said chalcogenide glass layers comprise a plurality of chalcogenide glass layers.
149. The system of claim 146 wherein one or more of said metal-containing layers comprises a plurality of metal-containing layers.
150. The system of claim 146 wherein one or more of said chalcogenide glass layers contains a metal dopant.
151. The system of claim 150 wherein said metal dopant comprises silver.
152. The system of claim 146 wherein each of said at least one first and second silver layers is an evaporated silver layer.
153. The method of claim 146 wherein each of said at least one first and second silver layers has a thickness of from about 50 \u212b to about 250 \u212b.
154. The method of claim 146 further comprising a third silver layer located on a side of said first metal-containing layer opposite the side on which said first silver layer is located, and a fourth silver layer located on a side of said second metal-containing layer opposite the side on which said second silver layer is located.
155. A memory element comprising:
a first electrode;
a second electrode; and
a plurality of chalcogenide glass layers, a plurality of metal-containing layers, and a plurality of silver layers between said first and second electrodes, each of said plurality of metal-containing layers being in contact with at least one of said plurality of silver layers, whereby said plurality of chalcogenide glass layers alternate with said metal-containing layers and said silver layers, with one of said chalcogenide glass layers in contact with said first electrode and another of said chalcogenide glass layers in contact with said second electrode.
156. The memory element of claim 155 wherein said plurality of metal-containing layers comprises one or more silver-selenide layers.
157. The memory element of claim 155 wherein one or more of said plurality of chalcogenide glass layers comprises a plurality of chalcogenide glass layers.
158. The memory element of claim 155 wherein one or more of said plurality of metal-containing layers comprises a plurality of metal-containing layers.
159. The memory element of claim 155 wherein one or more of said plurality of chalcogenide glass layers contains a metal dopant.
160. The memory element of claim 159 wherein said metal dopant comprises silver.
161. The memory element of claim 155 wherein each of said plurality of silver layers is an evaporated silver layer.
162. The memory element of claim 155 wherein each of said plurality of silver layers has a thickness of from about 50 \u212b to about 250 \u212b.
163. A method of forming a resistance variable memory element comprising:
forming a first electrode;
forming a second electrode; and
forming a plurality of chalcogenide glass layers, a plurality of metal-containing layers, and a plurality of silver layers between said first and second electrodes, each of said plurality of metal-containing layers being in contact with at least one of said plurality of silver layers, whereby said plurality of chalcogenide glass layers alternate with said metal-containing layers and said silver layers, with one of said chalcogenide glass layers in contact with said first electrode and another of said chalcogenide glass layers in contact with said second electrode.
164. The method of claim 163 wherein said plurality of metal-containing layers comprises one or more silver-selenide layers.
165. The method of claim 163 wherein one or more of said plurality of chalcogenide glass layers comprises a plurality of chalcogenide glass layers.
166. The method of claim 163 wherein one or more of said plurality of metal-containing layers comprises a plurality of metal-containing layers.
167. The method of claim 163 wherein one or more of said plurality of chalcogenide glass layers contains a metal dopant.
168. The method of claim 167 wherein said metal dopant comprises silver.
169. The method of claim 163 wherein each of said plurality of silver layers is an evaporated silver layer.
170. The method of claim 163 wherein each of said plurality of silver layers has a thickness of from about 50 \u212b to about 250 \u212b.