1. A computer program product comprising a computer readable storage medium having program instructions embodied therewith, the program instructions executable by a processor to cause the processor to perform a method comprising:
a compute node sensing the operating environment around the compute node during setup of the compute node and storing the operating environment sensed during setup as the predetermined operating environment;
the compute node tracking data stored by the compute node while the compute node is located within the predetermined operating environment;
the compute node sensing a current operating environment of the computer system at a point in time after setup and after data has been stored by the compute node;
the compute node determining whether the current operating environment is the same as a predetermined operating environment; and
the compute node wiping the data stored by the compute node while the compute node was located within the predetermined operating environment in response to determining that the current operating environment is not the same as the predetermined operating environment.
2. The computer program product of claim 1, wherein the step of the compute node sensing a current operating environment of the computer system, includes obtaining information about other compute nodes in the operating environment.
3. The computer program product of claim 2, wherein the information is selected from a media access control address and a host name.
4. The computer program product of claim 3, wherein the step of the compute node determining whether the sensed operating environment is the same as a predetermined operating environment stored by the compute node includes determining whether the compute node can still access the other compute nodes.
5. The computer program product of claim 1, wherein the step of the compute node sensing a current operating environment of the computer system, includes interrogating other compute nodes in the operating environment using an intelligent platform management interface command.
6. The computer program product of claim 1, wherein the step of the compute node sensing a current operating environment of the compute node, includes sensing one or more parameter of the operating environment selected from an ambient temperature, an acoustic signal and an image.
7. The computer program product of claim 1, wherein the step of the compute node sensing a current operating environment of the compute node, includes comparing a current correlation of system load and fan speed to a previous correlation of system load and fan speed.
8. The computer program product of claim 1, wherein the step of the compute node sensing a current operating environment of the compute node, includes obtaining a global positioning system signal representing a location of the compute node.
9. The computer program product of claim 1, wherein the step of the compute node sensing a current operating environment of the compute node, includes obtaining biometric data of a person near the compute node.
10. The computer program product of claim 1, wherein the step of the compute node determining whether the sensed operating environment is the same as a predetermined operating environment stored by the compute node includes determining whether the compute node is assigned the same IP address by a Dynamic Host Configuration Protocol server as the compute node was previously assigned.
11. The computer program product of claim 1, wherein the step of the compute node determining whether the sensed operating environment is the same as a predetermined operating environment stored by the compute node is performed each time the compute node is booted.
12. The computer program product of claim 1, wherein the step of the compute node determining whether the sensed operating environment is the same as a predetermined operating environment stored by the compute node is performed periodically at a predetermined interval.
13. The computer program product of claim 1, wherein the step of the compute node wiping data stored in the compute node includes:
reading a stored instruction identifying the data to be wiped.
14. The computer program product of claim 13, wherein the stored instruction is accessible to a basic input output system of the compute node, and the basic input output system initiates the step of the compute node wiping data stored in the compute node.
15. The computer program product of claim 13, wherein the stored instruction is accessible to a unified extensible firmware interface of the compute node, and the unified extensible firmware interface initiates the step of the compute node wiping data stored in the compute node.
16. The computer program product of claim 1, wherein the compute node includes a basis input output system, the method further comprising:
locking the basic input output system in response to determining that the sensed operating environment is not the same as the predetermined operating environment.
17. The computer program product of claim 1, wherein the step of the compute node wiping data stored in the compute node includes:
causing the compute node to revert to factory default settings.
18. The computer program product of claim 1, wherein the step of the compute node wiping data stored in the compute node includes:
deleting an encryption key necessary to read encrypted data stored on a data storage device accessible to the compute node.
19. The computer program product of claim 1, wherein the step of the compute node wiping data stored in the compute node includes:
destroying a data storage device that stores the data.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A nanopore device comprising:
a channel unit comprising a micro channel defined by a bottom surface and an insulator lateral wall; and
a cover unit covering the micro channel, wherein the cover unit comprises:
a nanopore extending through the cover unit and connected to the micro channel;
a first sourcedrain electrode disposed on an upper surface of the cover unit and adjacent to an inlet of the nanopore;
an opening extending through the cover unit and connected to the micro channel; and
a second sourcedrain electrode disposed on the upper surface of the cover unit and adjacent to the opening.
2. The nanopore device of claim 1, wherein the cover unit further comprises a gate electrode that surrounds the nanopore.
3. The nanopore device of claim 2, wherein the cover unit further comprises a gate insulating layer that covers the gate electrode on an internal wall of the nanopore.
4. The nanopore device of claim 2, further comprising:
a gate contact plug extending through the cover unit and electrically connected to the gate electrode; and
a contact unit disposed on the upper surface of the cover unit and electrically connected to the gate contact plug, the first sourcedrain electrode, and the second sourcedrain electrode through electrical wiring.
5. The nanopore device of claim 2, wherein thickness of the gate electrode is about 0.3 nm to about 0.4 nm, and an internal diameter of the nanopore is about 1 nm to about 1.5 nm in an area where the gate electrode is disposed.
6. The nanopore device of claim 1, wherein the cover unit further comprises:
a first solution reservoir that protrudes from the upper surface of the cover unit and surrounds the nanopore and the first sourcedrain electrode; and
a second solution reservoir that protrudes from the upper surface of the cover unit and surrounds the opening and the second sourcedrain electrode.
7. The nanopore device of claim 6, wherein the first solution reservoir and the second solution reservoir are each comprise a hydrophobic wall.
8. The nanopore device of claim 6, wherein the cover unit comprises a plurality of first solution reservoirs.
9. The nanopore device of claim 8, wherein the cover unit comprises a plurality of nanopores and a plurality of first sourcedrain electrodes that are respectively disposed in the plurality of first solution reservoirs.
10. The nanopore device of claim 8, wherein the second solution reservoir is disposed between the plurality of first solution reservoirs.
11. The nanopore device of claim 1, wherein the bottom surface comprises a semiconductor material.
12. The nanopore device of claim 1, further comprising at least one column connected between an upper surface of the bottom surface and a lower surface of the cover unit in the micro channel and supporting the cover unit.
13. The nanopore device of claim 1, wherein the cover unit comprises a stack having at least one insulating layer.
14. The nanopore device of claim 1, wherein the first sourcedrain electrode has a ring shape and surrounds the inlet of the nanopore.
15. The nanopore device of claim 1, wherein an opening area of the opening is greater than an opening area of the nanopore.
16. A method of fabricating a nanopore device, the method comprising:
sequentially stacking first, second, and third insulating layers on a semiconductor substrate comprising an active region and an insulator lateral wall region surrounding the active region;
forming an opening and a plurality of first via holes through the first, second, and third insulating layers to expose the active region;
forming a micro channel by etching a portion of the active region, which is below the first insulating layer, through the opening and the plurality of first via holes;
stacking a fourth insulating layer on the third insulating layer;
forming a nanopore through the first, second, third, and fourth insulating layers and connected to the micro channel; and
forming a first sourcedrain electrode adjacent to an inlet of the nanopore on the fourth insulating layer, and a second sourcedrain electrode adjacent to the opening on the fourth insulating layer.
17. The method of claim 16, wherein the sequential stacking of first, second, and third insulating layers comprises:
forming the first insulating layer on the semiconductor substrate;
forming a gate electrode on a portion of the first insulating layer;
forming a second insulating layer on the first insulating layer and covering the gate electrode;
forming the third insulating layer, having a different etch rate that of the second insulating layer, on the second insulating layer;
forming a second via hole through the third insulating layer and facing the gate electrode;
etching the second insulating layer to expose the gate electrode through the second via hole; and
filling a spacer in a space created by removing the second insulating layer.
18. The method of claim 17, wherein the gate electrode is formed over an interface between the active region and the insulator lateral wall.
19. The method of claim 17, wherein the gate electrode has a thickness of about 0.3 nm to about 0.4 nm.
20. The method of claim 17, wherein the first, second, and fourth insulating layers are formed of silicon oxide, and the third insulating layer is formed of silicon nitride.
21. The method of claim 17, wherein the spacer is the same material as the second insulating layer.
22. The method of claim 17, wherein
the plurality of first via holes are arranged along columns and rows at a regular interval, and
a barrier having a horizontal cross-sectional area that is greater than a size of each first via hole is formed between the plurality of first via holes.
23. The method of claim 22, wherein forming the micro channel comprises wet-etching the active region in an under-cut process to form at least one column below the barrier disposed between the plurality of first via holes.
24. The method of claim 17, wherein forming the nanopore comprises:
forming a mask layer on the fourth insulating layer and forming a mask pattern by etching the mask layer to remove a portion of the mask layer corresponding to the second via hole;
exposing the second via hole by etching the fourth insulating layer through the mask pattern;
forming a nanopore by sequentially etching the spacer, the gate electrode, and the first insulating layer through the mask pattern and the second via hole; and
removing the mask layer.
25. The method of claim 24, further comprising forming a gate insulating layer to cover at least the gate electrode on an internal wall of the nanopore.
26. The method of claim 24, wherein an internal diameter of the nanopore is about 1 nm to about 1.5 nm in an area where the gate electrode is disposed.
27. The method of claim 24, further comprising forming a gate contact plug that is electrically connected to the gate electrode by sequentially etching the fourth insulating layer, the third insulating layer, and the second insulating layer.
28. A method of analyzing a nucleic acid molecule comprising contacting the nanopore of the device of claim 1 with a sample comprising a nucleic acid, applying an electic current between the first and second sourcedrain electrodes, and detecting a change in the voltage between the first and second sourcedrain electrodes.
29. A method of analyzing a nucleic acid molecule comprising contacting the nanopore of the device of claim 2 with a sample comprising a nucleic acid, applying an electic current between the first and second sourcedrain electrodes, and detecting a change in voltage at the gate electrodes.
30. The method of claim 28, wherein the relative magnitude of a change in the voltage between the first and second sourcedrain electrodes indicates the relative size of a base of the nucleic acid passing through the nanopore.