1. A circuit comprising:
an on-chip gyrating circuit that generates a motion parameter based on motion of the circuit;
a global positioning system (GPS) receiver that receives a GPS signal and that generates GPS position data based on the GPS signal;
a processing module coupled to:
process the motion parameter to produce motion data;
generates position information based on at least one of the GPS position data and the motion data;
convert outbound data into an outbound symbol stream; and
convert an inbound symbol stream into inbound data; and
a wireless local area network (WLAN) transceiver section coupled to:
generate an outbound RF signal from the outbound symbol stream; and
convert an inbound RF signal into the inbound symbol stream.
2. The circuit of claim 1 wherein the processing module adjusts a receiver parameter of the GPS receiver based on the motion data.
3. The circuit of claim 1 wherein the processing module further generates a receive control signal in accordance with the motion data, wherein the wireless local area network transceiver is further operable to adjust a receive parameter based on the receive control signal, and wherein the receive parameter includes at least one of a receiver sensitivity, a protocol selection, a data rate, a packet length, a data payload length, a coding parameter, a contention period, and a back-off parameter.
4. The circuit of claim 1 wherein the processing module further generates an antenna control signal in accordance with the motion data and wherein the antenna control signal is coupled to an antenna to modify at least one of, an in-air beamforming phase, a diversity antenna selection, an antenna gain, a polarization antenna selection, a multi-input multi-output (MIMO) antenna structure, and a single-input single-output (SISO) antenna structure.
5. The circuit of claim 1 wherein the processing module further generates a transmit control signal in accordance with the motion data, wherein the wireless local area network transceiver is further operable to adjust a transmit parameter based on the transmit control signal, and wherein the transmit parameter includes at least one of a transmit power, a protocol selection, a data rate, a packet length, a data payload length, a coding parameter, a contention period, and a back-off parameter.
6. The circuit of claim 1 wherein the GPS receiver generates a GPS data indication that indicates a GPS data quality, wherein the processing module generates the position information based on estimated position data when the GPS data indication compares unfavorably to a first value and generates the position information based on the GPS position data when the GPS data indication compares favorably to the first value.
7. The circuit of claim 1 wherein the motion data includes a motion vector, wherein the processing module generates velocity information based on the motion vector when the GPS data indication compares unfavorably to a first value, and generates velocity information based on the GPS position data when the GPS data indication compares favorably to the first value.
8. The circuit of claim 1 wherein the wireless local area network transceiver includes position information in the outbound data and receives inbound data that includes control data.
9. The circuit of claim 8 wherein the processing module further generates a receive control signal in accordance with the control data, wherein the wireless local area network transceiver is further operable to adjust a receive parameter based on the receive control signal, and wherein the receive parameter includes at least one of a receiver sensitivity, a protocol selection, multi-input multi-output (MIMO) coefficients, a data rate, a packet length, a data payload length, a coding parameter, a contention period, and a back-off parameter.
10. The circuit of claim 8 wherein the processing module further generates an antenna control signal in accordance with the control data, wherein the antenna control signal is coupled to an antenna to modify at least one of, an in-air beamforming phase, a diversity antenna selection, an antenna gain, a polarization antenna selection, a multi-input multi-output (MIMO) antenna structure, and a single-input single-output (SISO) antenna structure.
11. The circuit of claim 8 wherein the processing module further generates a transmit control signal in accordance with the control data, wherein the wireless local area network transceiver is further operable to adjust a transmit parameter based on the transmit control signal, and wherein the transmit parameter includes at least one of a transmit power, a protocol selection, a data rate, a packet length, a data payload length, a coding parameter, a contention period, and a back-off parameter.
12. An integrated circuit (IC) comprising:
an on-chip gyrating circuit that generates a motion parameter based on motion of the IC, wherein the on-chip gyrating circuit is implemented with microelectromechanical systems (MEMS) technology;
a global positioning system (GPS) receiver that receives a GPS signal and that generates GPS position data based on the GPS signal;
a processing module, coupled to the on-chip gyrating circuit and the GPS transceiver, that processes the motion parameter to produce motion data and that generates position information based on the GPS position data and the motion data; and
a wireless local area network transceiver, coupled to the processing module, that generates an outbound RF signal that includes outbound data and that generates inbound data from an inbound RF signal.
13. The IC of claim 12 wherein the on-chip gyrating circuit includes one of:
a piezoelectric gyroscope;
a vibrating wheel gyroscope;
a tuning fork gyroscope;
a hemispherical resonator gyroscope; and
a rotating wheel gyroscope.
14. The IC of claim 12 wherein the IC is integrated in a package having a substrate and a first die and wherein the GPS transceiver and the on-chip gyrating circuit are implemented on the first die.
15. The IC of claim 12 wherein the IC is integrated in a package having a substrate, a first die and a second die and wherein the GPS transceiver and wireless local area network transceiver are implemented on the first die and the on-chip gyrating circuit is implemented on the second die.
16. The IC of claim 12 wherein the IC is integrated in a package having a substrate and a first die wherein the GPS transceiver, wireless local area network transceiver, processing module and the on-chip gyrating circuit are implemented on the first die.
17. The IC of claim 12 wherein the IC is integrated in a package having a substrate and a first die and a second die, and wherein the GPS transceiver, wireless local area network transceiver and processing module are implemented on the first die and the on-chip gyrating circuit is implemented on the second die.
18. A wireless communication device comprises:
an integrated circuit (IC) that includes:
a package substrate that supports an on-chip gyrating circuit that generates the motion parameter based on motion of the wireless communication device, and wherein the package substrate further supports a die that supports:
a GPS receiver that receives a GPS signal and that generates GPS position data based on the GPS signal;
a processing module, coupled to the on-chip gyrating circuit and the GPS transceiver, that processes the motion parameter to produce motion data and that generates position information based on the GPS position data and the motion data; and
a wireless local area network transceiver that generates an outbound RF signal that includes outbound data and that generates voice inbound data from an inbound RF signal; and
an antenna structure coupled to receive the inbound RF signal and to transmit the outbound RF signal.
19. The circuit of claim 18 wherein the processing module further generates a receive control signal in accordance with the motion data, and wherein the wireless local area network transceiver is further operable to adjust a receive parameter based on the receive control signal.
20. The circuit of claim 19 wherein the receive parameter includes at least one of a receiver sensitivity, a protocol selection, a data rate, a packet length, a data payload length, a coding parameter, a contention period, and a back-off parameter.
21. The circuit of claim 18 wherein the processing module further generates an antenna control signal in accordance with the motion data.
22. The circuit of claim 21 wherein the antenna control signal is coupled to an antenna to modify at least one of, an in-air beamforming phase, a diversity antenna selection, an antenna gain, a polarization antenna selection, a multi-input multi-output (MIMO) antenna structure, and a single-input single-output (SISO) antenna structure
23. The circuit of claim 18 wherein the processing module further generates a transmit control signal in accordance with the motion data and wherein the wireless local area network transceiver is further operable to adjust a transmit parameter based on the transmit control signal.
24. The circuit of claim 23 wherein the transmit parameter includes at least one of a transmit power, a protocol selection, a data rate, a packet length, a data payload length, a coding parameter, a contention period, and a back-off parameter.
25. The circuit of claim 18 wherein the wireless local area network transceiver includes position information in the outbound data and receives inbound data from an access point that includes control data.
26. The circuit of claim 25 wherein the processing module further generates a receive control signal in accordance with the control data and wherein the wireless local area network transceiver is further operable to adjust a receiver parameter based on the receive control signal.
27. The circuit of claim 26 wherein the receive parameter includes at least one of a receiver sensitivity, a protocol selection, a data rate, a packet length, a data payload length, a coding parameter, a contention period, and a back-off parameter.
28. The circuit of claim 25 wherein the processing module further generates an antenna control signal in accordance with the control data and wherein the antenna control signal is coupled to an antenna to modify at least one of, an in-air beamforming phase, a diversity antenna selection, an antenna gain, a polarization antenna selection, a multi-input multi-output (MIMO) antenna structure, and a single-input single-output (SISO) antenna structure.
29. The circuit of claim 25 wherein the processing module further generates a transmit control signal in accordance with the control data and wherein the wireless local area network transceiver is further operable to adjust a transmit parameter based on the transmit control signal.
30. The circuit of claim 29 wherein the transmit parameter includes at least one of a transmit power, a protocol selection, a data rate, a packet length, a data payload length, a coding parameter, a contention period, and a back-off parameter.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A method for manufacturing a memory structure, comprising:
forming a plurality of stacks on a substrate, wherein the stacks are separated from each other by a plurality of trenches, and each of the stacks comprises alternately stacked conductive stripes and insulating stripes;
forming a plurality of memory layers conformally covering the stacks respectively;
forming a conductive material in the trenches and on the stacks, the conductive material having a top portion;
forming one or more holes in the conductive material in each of the trenches; and
defining a plurality of predetermined regions for respectively forming a plurality of conductive lines in the top portion of the conductive material, wherein each of the predetermined regions comprises a first predetermined region and a second predetermined region connected to each other, the first predetermined region extends along a direction perpendicular to an extending direction of the stacks, and the second predetermined region extends along the extending direction of the stacks.
2. The method according to claim 1, wherein the one or more holes in each of the trenches are arranged in a matrix, or arranged to constitute a triangle-like in layout design.
3. The method according to claim 1, wherein said defining the predetermined regions is carried out before said forming the one or more holes.
4. The method according to claim 1, wherein said defining the predetermined regions is carried out after said forming the one or more holes.
5. The method according to claim 1, wherein lengths of the first predetermined regions and the second predetermined regions are sequentially increased.
6. The method according to claim 1, further comprises:
removing the top portion of the conductive material that is not in the predetermined regions; and
forming the conductive lines on the top portion of the conductive material remained in the predetermined regions.
7. The method according to claim 6, further comprises:
before said removing the top portion of the conductive material that is not in the predetermined regions, filling an insulating material into the one or more holes in each of the trenches.
8. The method according to claim 7, wherein said removing the top portion of the conductive material that is not in the predetermined regions comprises a cutting step and a removing step, the cutting step comprises removing portions of the top portion of conductive material and portions of the memory layers on the stacks along the direction perpendicular to the extending direction of the stacks, and the removing step comprises removing remained portions of the top portion of conductive material that is not in the predetermined regions.
9. The method according to claim 6, wherein the first predetermined regions of adjacent two of the predetermined regions are connected to each other by an extending portion of the second predetermined region of one of the adjacent two of the predetermined regions, and the top portion of the conductive material in the extending portion is removed by a cutting step.
10. The method according to claim 6, wherein the first predetermined regions of adjacent two of the predetermined regions are connected to each other by an extending portion of the second predetermined region of one of the adjacent two of the predetermined regions and an extending portion of the second predetermined region of another one of the predetermined regions, and the top portion of the conductive material in the extending portion of the second predetermined region of one of the adjacent two of the predetermined regions and in the extending portion of the second predetermined region of the another one of the predetermined regions is removed by a cutting step.
11. The method according to claim 1, wherein the conductive lines are formed of silicide.
12. The method according to claim 1, wherein the conductive stripes in the stacks are used as bit lines, and the conductive lines are used as word lines.
13. The method according to claim 1, wherein the conductive stripes in the stacks are used as word lines, and the conductive lines are used as bit lines.
14. A memory structure, comprising:
a substrate;
a plurality of stacks positioned on the substrate, wherein the stacks are separated from each other by a plurality of trenches, and each of the stacks comprises alternately stacked conductive stripes and insulating stripes;
a plurality of memory layers conformally covering the stacks respectively;
a conductive material positioned in the trenches and on the stacks, wherein the conductive material in the trenches forms one or more holes in each of the trenches; and
a plurality of conductive lines positioned on the conductive material, wherein each of the conductive lines comprises a first portion and a second portion connected to each other, the first portion extends along a direction perpendicular to an extending direction of the stacks, and the second portion extends along the extending direction of the stacks.
15. The memory structure according to claim 14, wherein the one or more holes in each of the trenches are arranged in a matrix.
16. The memory structure according to claim 14, wherein the one or more holes in each of the trenches are arranged to constitute a triangle-like in layout design.
17. The memory structure according to claim 14, wherein lengths of the first portions and the second portions of the conductive lines are sequentially increased.
18. The memory structure according to claim 14, wherein the conductive lines are formed of silicide.
19. The memory structure according to claim 14, wherein the conductive stripes in the stacks are used as bit lines, and the conductive lines are used as word lines.
20. The memory structure according to claim 14, wherein the conductive stripes in the stacks are used as word lines, and the conductive lines are used as bit lines.