1. A method for producing an optical component made from quartz glass, said method comprising: supplying in vertical orientation to a heating zone a coaxial arrangement comprising a core rod surrounded by a quartz-glass cladding tube having therein an evacuable inner bore, softening the coaxial arrangement in the heating zone zonewise so as to form a drawing bulb, and elongating the coaxial arrangement to obtain the optical component, wherein the core rod comprises at least two core rod sections arranged loosely one on top of another in the inner bore the upper core rod section being supported in a holding or supporting portion of the cladding tube provided above the drawing bulb.
2. The method according to claim 1, wherein the upper core rod section is suspended from the holding or supporting portion.
3. The method according to claim 2, wherein the upper core rod section is provided at an upper end thereof with an outer collar resting on an upper face of the cladding tube.
4. The method according to claim 2, wherein a holding body supported in a wall of the cladding tube engages an upper end of the upper core rod section.
5. The method according to claim 1, wherein the upper core rod section is supported by the holding or supporting portion.
6. The method according to claim 5, wherein the holding or supporting portion is shaped in the form of a necking of the inner bore of the cladding tube, and the upper core rod section rests directly or indirectly on the necking of the inner bore.
7. The method according to claim 6, wherein the necking is configured as a surrounding inner bead of the cladding tube.
8. The method according to claim 6, wherein the cladding tube is produced by butt welding tube sections, the necking being simultaneously formed in an area of a joint during the welding.
9. The method according to claim 5, wherein the upper core rod section rests on a lower core rod section directly or indirectly, a weight of the lower core rod section being supported by the holding or supporting portion.
10. The method according to claim 9, wherein the lower core rod section is suspended from the holding or supporting portion.
11. The method according to claim 1, further comprising providing structure for preventing floating of core rod sections during elongation.
12. The method according to claim 11, wherein the structure preventing floating is formed by a necking of the inner bore.
13. The method according to claim 1, wherein the cladding tube comprises an inner cylinder that surrounds the core rod and is provided with the holding or supporting portion, and an outer cylinder which surrounds the inner cylinder.
14. The method according to claim 13, wherein the holding or supporting portion is formed as a necking of an inner cylinder bore.
15. The method according to claim 13, wherein the upper core rod section is suspended from the holding or supporting portion.
16. The method according to claim 1, wherein the cladding tube comprises an inner cylinder surrounding the core rod and an outer cylinder surrounding the inner cylinder and is provided with the holding or supporting portion.
17. The method according to claim 16, wherein the inner cylinder comprises at least one lower longitudinal segment and an upper longitudinal segment which is provided at a lower end thereof with a narrowing inner bore on which the upper core rod section is positioned.
18. The method according to claim 17, wherein the holding or supporting portion is formed in the shape of a necking of the inner bore of the outer cylinder on which the upper longitudinal segment is positioned with the lower end thereof.
19. The method according to claim 16, wherein the upper core rod section is fixed in the inner cylinder which is provided at the upper end thereof with an outer collar that grips over the holding or supporting portion.
20. The method according claim 1, wherein the lower core rod section is supported at a place different from the holding or supporting portion.
21. The method according to claim 1, wherein the lower core rod section is supported by the holding or supporting portion.
22. The method according to claim 1, wherein an intermediate piece of quartz glass is arranged inside the cladding tube in an area of the holding or supporting portion.
23. The method according to claim 22, wherein the intermediate piece is provided with gas passage openings.
24. The method according to claim 1, wherein the cladding tube has a length of more than 4 m.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A delay locked loop circuit comprising:
a clock receiver for inputting an external clock and outputting an inverted clock and a reference clock, the inverted clock being an inverted version of the external clock;
a multiplexer for receiving the external clock and the inverted clock and selectively outputting any one of the received clocks;
a first delay for delaying an output signal from the multiplexer by a first desired delay period;
a clock driver for receiving an output signal from the first delay and generating an internal clock;
a second delay for delaying an output signal from the clock driver by a second desired delay period to output a feedback clock; and
a phase detector for comparing a phase of the feedback clock from the second delay with that of the reference clock from the clock receiver and outputting a first phase control signal for control of a selection operation of the multiplexer and a second phase control signal for control of a delay operation of the first delay in accordance with a result of the comparison.
2. The delay locked loop circuit as set forth in claim 1, further comprising:
a multiplexer controller for controlling the operation of the multiplexer in response to the first phase control signal; and
a clock delay controller for controlling the operation of the first delay in response to the second phase control signal.
3. The delay locked loop circuit as set forth in claim 2, wherein the multiplexer controller controls the multiplexer according to a level of the first phase control signal such that the multiplexer selects any one of the external clock and inverted clock in an initial operation of the delay locked loop circuit.
4. The delay locked loop circuit as set forth in claim 2, wherein the clock delay controller increases or reduces the first delay period according to a level of the second phase control signal.
5. The delay locked loop circuit as set forth claim 1, wherein the phase detector includes:
a first latch for latching status information of the reference clock synchronously with the feedback clock;
a first buffer for buffering an output signal from the first latch;
a delay for delaying the feedback clock by a predetermined period to output a delayed feedback clock;
a second latch for latching the status information of the reference clock synchronously with the delayed feedback clock;
a second buffer for buffering an output signal from the second latch; and
a logic unit for performing a logical operation with respect to an output signal from the first buffer and an output signal from the second buffer.
6. The delay locked loop circuit as set forth in claim 5, wherein the output signal from the first buffer is the first phase control signal, and an output signal from the logic unit is the second phase control signal.
7. The delay locked loop circuit as set forth in claim 5, wherein the logic unit performs a logical sum operation.
8. The delay locked loop circuit as set forth in claim 5, wherein the first latch latches the status information of the reference clock at a rising edge or falling edge of the feedback clock.
9. The delay locked loop circuit as set forth in claim 5, wherein the second latch latches the status information of the reference clock at a rising edge or falling edge of the delayed feedback clock.
10. The delay locked loop circuit as set forth in claim 8, wherein the first latch and the second latch are flip-flops.
11. The delay locked loop circuit as set forth in claim 5, wherein the first buffer and the second buffer are inverting buffers.
12. The delay locked loop circuit as set forth in claim 1, wherein the output signal from the clock driver to the second delay is the internal clock.
13. The delay locked loop circuit as set forth in claim 1, wherein the reference clock is in phase with the external clock.
14. The delay locked loop circuit as set forth in claim 1, further comprising a duty corrector for correcting the duty of the output signal from the first delay and supplying the resulting signal to the clock driver.
15. A delay locked loop circuit comprising:
a first phase control signal for controlling selection of any one of an external clock and an inverted clock from an external clock receiver, the inverted clock being an inverted version of the external clock;
a second phase control signal for controlling setting of a delay period of a selected one of the external clock and inverted clock; and
a phase detector for receiving a reference clock and a feedback clock of a delay locked loop and generating the first and second phase control signals based on the reference clock and feedback clock, wherein the first phase control signal and the second phase control signal are generated along different paths in the phase detector.
16. The delay locked loop circuit as set forth in claim 15, further comprising:
a multiplexer for receiving the external clock and the inverted clock and selectively outputting any one of the received clocks;
a delay for delaying an output signal from the multiplexer by a desired delay period;
a multiplexer controller for controlling an operation of the multiplexer in response to the first phase control signal; and
a clock delay controller for controlling an operation of the delay in response to the second phase control signal.
17. The delay locked loop circuit as set forth in claim 16, wherein the multiplexer controller controls the multiplexer according to a level of the first phase control signal such that the multiplexer selects any one of the external clock and inverted clock in an initial operation of the delay locked loop circuit.
18. The delay locked loop circuit as set forth in claim 16, wherein the clock delay controller increases or reduces the delay period according to a level of the second phase control signal.
19. The delay locked loop circuit as set forth in claim 15, wherein the phase detector includes:
a first latch for latching status information of the reference clock synchronously with the feedback clock;
a first buffer for buffering an output signal from the first latch;
a delay for delaying the feedback clock by a predetermined period to output a delayed feedback clock;
a second latch for latching the status information of the reference clock synchronously with the delayed feedback clock;
a second buffer for buffering an output signal from the second latch; and
a logic unit for performing a logical operation with respect to an output signal from the first buffer and an output signal from the second buffer.
20. The delay locked loop circuit as set forth in claim 19, wherein the output signal from the first buffer is the first phase control signal, and an output signal from the logic unit is the second phase control signal.
21. The delay locked loop circuit as set forth in claim 19, wherein the logic unit performs a logical sum operation.
22. The delay locked loop circuit as set forth in claim 19, wherein the first latch latches the status information of the reference clock at a rising edge or falling edge of the feedback clock.
23. The delay locked loop circuit as set forth in claim 19, wherein the second latch latches the status information of the reference clock at a rising edge or falling edge of the delayed feedback clock.
24. The delay locked loop circuit as set forth in claim 22, wherein the first latch and the second latch are flip-flops.
25. The delay locked loop circuit as set forth in claim 19, wherein the first buffer and the second buffer are inverting buffers.
26. The delay locked loop circuit as set forth in claim 19, wherein the reference clock is in phase with the external clock.