1. A power inverter comprising:
a plurality of power conversion elements that convert DC power supplied from a first DC power source into AC power used to drive an electrical motor;
a first control circuit to which power is supplied from a second DC power source and which outputs a first control signal configured to control an operation of the plurality of power conversion elements;
an electric storage circuit that stores the DC power by performing charging based on AC power generated by the electrical motor;
a power source circuit that supplies power based on the first DC power source or the DC power supplied from the electric storage circuit;
a voltage measurement circuit that measures a voltage of the electric storage circuit;
a second control circuit to which the power is supplied from the power source circuit and which determines whether the second DC power source is normal and outputs a second control signal configured to control the operation of the plurality of power conversion elements based on the voltage of the electric storage circuit measured by the voltage measurement circuit, when determining that the second DC power source is not normal; and
a driving circuit to which the power is supplied from the power source circuit and which outputs a driving signal configured to operate the plurality of power conversion elements based on the first or second control signal,
wherein the plurality of power conversion elements are one of power conversion elements of an upper arm connected to a high-voltage side of the first DC power source and power conversion elements of a lower arm connected to a low-voltage side of the first DC power source, and a plurality of series circuits in which the power conversion elements of the upper arm and the power conversion elements of the lower arm are connected in series are connected in parallel to the electric storage circuit with respect to the first DC power source, and
wherein, when the voltage of the electric storage circuit is greater than a predetermined first voltage value, the second control circuit outputs the second control signal configured to turn on all of one of the power conversion elements of the upper arm and the power conversion elements of the lower arm and turn off all of the other thereof.
2. The power inverter according to claim 1, wherein, when the voltage of the electric storage circuit is equal to or less than a predetermined second voltage value lower than the first voltage value, the second control circuit outputs the second control signal configured to turn off all of the power conversion elements of the upper arm and the power conversion elements of the lower arm.
3. The power inverter according to claim 1, wherein, when the second control circuit controls the second control signal and determines that the second DC power source is normal, the second control circuit interrupts the control on the second control signal.
4. The power inverter according to claim 1, further comprising:
a controlling signal output circuit that outputs a controlling signal indicating whether the second control circuit controls the second control signal to the first control circuit.
5. The power inverter according to claim 4, wherein the first control circuit does not output the first control signal, when the controlling signal output circuit outputs the controlling signal indicating that the second control circuit controls the second control signal.
6. The power inverter according to claim 1, wherein the voltage measurement circuit is realized using a microcomputer that is operated by the power supplied from the power source circuit.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A method for image processing, the method comprising:
performing by one or more processors andor circuits within an image processing device:
combining results from a first video noise reduction operation and results from a second video noise reduction operation based on a first combination operation, wherein said second video noise reduction operation is different from said first video noise reduction operation;
selecting said first combination operation to be a first addition operation, a first maximum value operation, or a first minimum value operation based on a sign of said results from said first video noise reduction operation and a sign of said results from said second video noise reduction operation; and
generating a first pixel correction value based on results of said selected first combination operation.
2. The method according to claim 1, comprising correcting at least one pixel value utilizing said generated first pixel correction value.
3. The method according to claim 1, comprising selecting said first minimum value operation when said results from said first noise reduction operation and said results from said second noise reduction operation are both negative.
4. The method according to claim 1, comprising selecting said first maximum value operation when said results from said first noise reduction operation and said results from said second noise reduction operation are both positive.
5. The method according to claim 1, comprising selecting said first addition operation when said results from said first noise reduction operation and said results from said second noise reduction operation have different signs.
6. The method according to claim 1, wherein said results from said first noise reduction operation correspond to results from a horizontal block noise reduction operation.
7. The method according to claim 1, wherein said results from said second noise reduction operation correspond to results from a vertical block noise reduction operation.
8. The method according to claim 1, comprising:
combining said generated first pixel correction value and results from a third video noise reduction operation based on a second combination operation;
selecting said second combination operation to be a second addition operation, a second maximum value operation, or a second minimum value operation based on a sign of said generated first pixel correction value and a sign of said results from said third video noise reduction operation; and
generating a second pixel correction value based on results of said selected second combination operation.
9. The method according to claim 8, comprising correcting at least one pixel value utilizing said generated second pixel correction value.
10. The method according to claim 8, comprising selecting said second minimum value operation when said generated first pixel correction value and said results from said third noise reduction operation are both negative.
11. The method according to claim 8, comprising selecting said second maximum value operation when said generated first pixel correction value and said results from said third noise reduction operation are both positive.
12. The method according to claim 8, comprising selecting said second addition operation when said generated first pixel correction value and said results from said third noise reduction operation have different signs.
13. The method according to claim 8, wherein said results from said third noise reduction operation correspond to results from a mosquito noise reduction operation.
14. A system for image processing, the system comprising:
one or more circuits that are operable to combine results from a first video noise reduction operation and results from a second video noise reduction operation based on a first combination operation, wherein said second video noise reduction operation is different from said first video noise reduction operation;
said one or more circuits are operable to select said first combination operation to be a first addition operation, a first maximum value operation, or a first minimum value operation based on a sign of said results from said first video noise reduction operation and a sign of said results from said second video noise reduction operation; and
said one or more circuits are operable to generate a first pixel correction value based on results of said selected first combination operation.
15. The system according to claim 14, wherein said one or more circuits are operable to correct at least one pixel value utilizing said generated first pixel correction value.
16. The system according to claim 14, wherein said one or more circuits are operable to select said first minimum value operation when said results from said first noise reduction operation and said results from said second noise reduction operation are both negative.
17. The system according to claim 14, wherein said one or more circuits are operable to select said first maximum value operation when said results from said first noise reduction operation and said results from said second noise reduction operation are both positive.
18. The system according to claim 14, wherein said one or more circuits are operable to select said first addition operation when said results from said first noise reduction operation and said results from said second noise reduction operation have different signs.
19. The system according to claim 14, wherein said results from said first noise reduction operation correspond to results from a horizontal block noise reduction operation.
20. The system according to claim 14, wherein said results from said second noise reduction operation correspond to results from a vertical block noise reduction operation.
21. The system according to claim 14, wherein:
said one or more circuits are operable to combine said generated first pixel correction value and results from a third video noise reduction operation based on a second combination operation;
said one or more circuits are operable to select said second combination operation to be a second addition operation, a second maximum value operation, or a second minimum value operation based on a sign of said generated first pixel correction value and a sign of said results from said third video noise reduction operation; and
said one or more circuits are operable to generate a second pixel correction value based on results of said selected second combination operation.
22. The system according to claim 21, correct at least one pixel value utilizing said generated second pixel correction value.
23. The system according to claim 21, wherein said one or more circuits are operable to select said second minimum value operation when said generated first pixel correction value and said results from said third noise reduction operation are both negative.
24. The system according to claim 21, wherein said one or more circuits are operable to select said second maximum value operation when said generated first pixel correction value and said results from said third noise reduction operation are both positive.
25. The system according to claim 21, wherein said one or more circuits are operable to select said second addition operation when said generated first pixel correction value and said results from said third noise reduction operation have different signs.
26. The system according to claim 21, wherein said results from said third noise reduction operation correspond to results from a mosquito noise reduction operation.