1. A structure comprising:
at least one field effect transistor having a gate stack disposed between raised source drain structures that are adjacent to the gate stack, the gate stack and raised source drain structures being disposed on a surface of a semiconductor material, where the surface of the semiconductor material is a surface of a silicon-on-insulator layer disposed over a layer of buried oxide;
a layer of field dielectric overlying the gate stack and raised source drain structures; and
first contact metal and second contact metal extending through the layer of field dielectric, the first contact metal terminating in a first trench formed through a top surface of a first raised source drain structure, the second contact metal terminating in a second trench formed through a top surface of a second raised source drain structure, each trench comprising silicide formed on sidewalls and a bottom surface of at least a portion of the trench, where
the bottom surface of each trench extends at least to the layer of buried oxide.
2. The structure of claim 1, where the contact metal is comprised of a metal selected to exhibit one of tensile stress or compressive stress; and where the layer of field dielectric is comprised of a material selected to exhibit tensile stress when the selected contact metal exhibits tensile stress, and where the layer of field dielectric is comprised of a material selected to exhibit compressive stress when the contact metal exhibits compressive stress.
3. The structure of claim 1, where the at least one field effect transistor is one of a logic field effect transistor or a memory field effect transistor.
4. The structure of claim 1, where the raised source drain structures are in-situ doped raised source drain structures having faceted edges.
5. The structure of claim 1, where the raised source drain structures are in-situ doped raised source drain structures having non-faceted edges.
6. The structure of claim 1, further comprising silicide disposed on a gate conductor.
7. The structure of claim 1, where the silicide is comprised of one of nickel silicide, platinum silicide and titanium silicide.
8. A structure comprising:
at least one field effect transistor having a gate stack disposed between raised source drain structures, the gate stack and raised source drain structures being disposed on a surface of a semiconductor material, each raised source drain structure having a width and a height from the surface of the semiconductor material;
first contact metal terminating in a first trench formed through a top surface of a first raised source drain structure along substantially an entire width of the first raised source drain structure and extending into the first raised source drain structure by a distance substantially equal to the height of the first raised source drain structure, the first contact metal forming a bar-shaped contact to the first raised source drain structure; and
second contact metal terminating in a second trench formed through a top surface of a second raised source drain structure along substantially an entire width of the second raised source drain structure and extending into the second raised source drain structure by a distance substantially equal to the height of the second raised source drain structure, the second contact metal forming a bar-shaped contact to the second raised source drain structure; where
each of the first trench and the second trench comprises silicide formed on sidewalls and a bottom surface of at least a portion of the trench.
9. The structure of claim 8, where the contact metal exhibits one of tensile stress or compressive stress.
10. The structure of claim 8, further comprising a layer of field dielectric material that at least partially overlies the gate stack and raised source drain structures, where the layer of field dielectric material is configured to exhibit tensile stress when the contact metal exhibits tensile stress, and where the layer of field dielectric material is configured to exhibit compressive stress when the contact metal exhibits compressive stress.
11. The structure of claim 8, where the at least one field effect transistor is one of a logic field effect transistor or a memory field effect transistor.
12. The structure of claim 8, where the raised source drain structures are formed as in-situ doped raised source drain structures having faceted edges.
13. The structure of claim 8, where the raised source drain structures are formed as in-situ doped raised source drain structures having non-faceted edges.
14. The structure of claim 8, further comprising silicide disposed on a gate conductor.
15. A structure comprising:
at least one field effect transistor having a gate stack disposed between raised source drain structures, the gate stack being disposed over a channel region, the gate stack and raised source drain structures being disposed on a surface of a semiconductor material, each raised source drain structure having a width and a height from the surface of the semiconductor material;
first contact metal terminating in a first trench formed through a top surface of a first raised source drain structure along a portion of a width of the first raised source drain structure and extending into the first raised source drain structure, the first contact metal forming a contact stud to the first raised source drain structure;
second contact metal terminating in a second trench formed through a top surface of a second raised source drain structure along a portion of a width of the second raised source drain structure and extending into the second raised source drain structure, the second contact metal forming a contact stud to the second raised source drain structure; and
a layer of field dielectric material disposed over at least the first trench and the second trench and filling those portions of the first trench not occupied by the first contact metal and those portions of the second trench not occupied by the second contact metal, said layer of field dielectric being selected to impart one of a tensile stress or compressive stress to said channel region.
16. The structure of claim 15, where each of the first trench and the second trench comprises silicide formed on sidewalls and a bottom surface of at least a portion of the trench.
17. The structure of claim 15, where the contact metal also exhibits one of tensile stress or compressive stress.
18. The structure of claim 15, where the at least one field effect transistor is one of a logic field effect transistor or a memory field effect transistor.
19. The structure of claim 15, where the raised source drain structures are formed as in-situ doped raised source drain structures having one of faceted edges or non-faceted edges.
20. The structure of claim 16, where the first trench extends into the first raised source drain structure by a distance substantially equal to the height of the first raised source drain structure, and where the second trench extends into the second raised source drain structure by a distance substantially equal to the height of the second raised source drain structure.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A method for efficiently processing write data from a storage controller to a striped storage volume, comprising:
receiving, by the storage controller, a host write request comprising a host write request size;
calculating, by the storage controller, that a time to fill a stripe comprising the host write request is not less than a host guaranteed write time; and
processing, by the storage controller, the host write request as a write-through host write request,
wherein the time to fill the stripe is a size of the stripe divided by a data rate of a corresponding host write stream comprising the host write request, wherein the host guaranteed write time is the maximum latency that the storage controller guarantees host write requests are committed to one of a write cache and the striped storage volume.
2. The method of claim 1, wherein the host write request is not stored in the write cache, wherein write-through host write requests are stored directly to the striped storage volume.
3. The method of claim 2, wherein the corresponding host write stream is a set of LBA-sequential host write requests that are one of increasing and decreasing in LBA over time.
4. The method of claim 2, wherein after receiving the host write request and before calculating the time to fill the stripe comprising the host write request, the method further comprising:
determining, by the storage controller, if the host write request fits into an existing host write stream, wherein:
if the host write request does not fit into an existing host write stream, then:
creating, by the storage controller, a new host write stream comprising:
a time stamp identifying the time the new host write stream is created;
a current burst length equal to the host write request size; and
a stream window corresponding to a starting LBA of the host write request, wherein the stream window comprises a range of LBAs greater than the host write request;
if the host write request fits into an existing host write stream, then:
updating, by the storage controller, host write stream metadata corresponding to the host write request,
wherein the corresponding host write stream is one of an existing host write stream and the new host write stream.
5. The method of claim 4, wherein determining if the host write request fits into an existing host write stream comprises:
determining, by the storage controller, if a starting LBA of the host write request is within a stream window for an existing host write stream,
wherein if the starting LBA of the host write request is within a stream window for an existing host write stream then the host write request fits into an existing host write stream, wherein if the starting LBA of the host write request is not within a stream window for an existing host write stream then the host write request does not fit into an existing host write stream.
6. The method of claim 4, wherein updating host write stream metadata corresponding to the host write request comprises:
calculating, by the storage controller, an elapsed time for the corresponding host write stream; and
determining, by the storage controller, if a current burst comprises the host write request, wherein the corresponding host write stream comprises the current burst;
if the current burst comprises the host write request, then:
incrementing, by the storage controller, a current burst length by the host write request size; and
if the current burst does not comprise the host write request, then:
storing, by the storage controller, the elapsed time and the host write request size to a storage controller memory; and
calculating the data rate for the corresponding host write stream.
7. The method of claim 6, wherein the elapsed time identifies the time since the selected host write stream received a most recent host write request, wherein the elapsed time comprises the difference between a current time and the time last hit for the corresponding host write stream.
8. The method of claim 6, wherein calculating the data rate for the corresponding host write stream comprises calculating a weighted average of a predetermined number of most recent time since last burst values, wherein more recent time since last burst values provide a greater weighting to the weighted average than less recent time since last burst values, wherein a time since last burst value is the time between the last host write request of a first burst and the first host write request of a next sequential burst following the first burst.
9. The method of claim 6, wherein determining if the current burst comprises the host write request comprises:
comparing, by the storage controller, the elapsed time to a predetermined time, wherein the predetermined time identifies the maximum latency for host write requests to be within the current burst,
wherein if the elapsed time is not greater than the predetermined time, then the current burst comprises the host write request,
wherein if the elapsed time is greater than the predetermined time, then the current burst does not comprise the host write request.
10. A storage controller for efficiently processing write data from one or more host computers to a striped storage volume comprising one or more striped storage devices, comprising:
a processor; and
a memory, coupled to the processor, the memory comprising:
a write cache; and
a host guaranteed write time, wherein the host guaranteed write time is the maximum latency that the storage controller guarantees host write requests are committed to one of the write cache and the striped storage volume;
wherein the storage controller receives a host write request comprising a host write request size, calculates that a time to fill a stripe comprising the host write request is not less than the host guaranteed write time, and processes the host write request as a write-through host write request, wherein the time to fill the stripe is a size of a stripe comprising the host write request divided by a data rate of a corresponding host write stream comprising the host write request.
11. The storage controller of claim 10, wherein the host write request is not stored in the write cache, wherein write-through host write requests are stored directly to the striped storage volume.
12. The storage controller of claim 11, wherein the corresponding host write stream is a set of LBA-sequential host write requests that are one of increasing and decreasing in LBA over time.
13. The storage controller of claim 11, wherein after the storage controller receives the host write request and before the storage controller calculates the time to fill the stripe comprising the host write request, the storage controller determines if the host write request fits into an existing host write stream, wherein if the host write request does not fit into an existing host write stream, then the storage controller creates a new host write stream comprising:
a time stamp identifying the time the new host write stream is created;
a current burst length equal to the host write request size, and a stream window corresponding to a starting LBA of the host write request;
wherein if the host write request fits into an existing host write stream, then the storage controller updates host write stream metadata corresponding to the host write request.
14. The storage controller of claim 13, wherein the storage controller determines if the host write request fits into an existing host write stream comprises the storage controller determines if a starting LBA of the host write request is within a stream window for an existing host write stream, wherein if the starting LBA of the host write request is within a stream window for an existing host write stream then the host write request fits into an existing host write stream, wherein if the starting LBA of the host write request is not within a stream window for an existing host write stream then the host write request does not fit into an existing host write stream.
15. The storage controller of claim 13, wherein the storage controller updates host write stream metadata corresponding to the host write request comprises the storage controller calculates an elapsed time for the selected host write stream, and determines if a current burst comprises the host write request, wherein the corresponding host write stream comprises the current burst, wherein if the current burst comprises the host write request, then the storage controller increments a current burst length by the host write request size, wherein if the current burst does not comprise the host write request, then the storage controller stores the elapsed time and the host write request size to a storage controller memory and calculates the data rate for the corresponding host write stream.
16. The storage controller of claim 15, wherein the elapsed time identifies the time since the corresponding host write stream received a most recent host write request, wherein the elapsed time comprises the difference between a current time and the time last hit for the corresponding host write stream.
17. The storage controller of claim 15, wherein the storage controller calculates the data rate for the corresponding host write stream comprises the storage controller calculates a weighted average of a predetermined number of most recent time since last burst values, wherein more recent time since last burst values provide a greater weighting to the weighted average than less recent time since last burst values, wherein a time since last burst value is the time between the last host write request of a first burst and the first host write request of a next sequential burst following the first burst.
18. The storage controller of claim 17, wherein the storage controller determines if the current burst comprises the host write request comprises the storage controller compares the elapsed time to a predetermined time, wherein the predetermined time identifies the maximum latency for host write requests to be within the current burst, wherein if the elapsed time is not greater than the predetermined time, then the current burst comprises the host write request, wherein if the elapsed time is greater than the predetermined time, then the current burst does not comprise the host write request.
19. A system for efficiently transferring write data to storage devices, comprising:
a host computer;
a storage controller, coupled to the host computer, comprising:
a processor; and
a memory, coupled to the processor, comprising a write cache; and
a striped volume comprising one or more storage devices, coupled to the storage controller,
wherein the host computer transfers a host write request to the storage controller, wherein the host write request is directed to a stripe of the striped storage volume, wherein in response to the host computer transfers the host write request to the storage controller, the storage controller calculates that a time to fill the stripe is greater than a host guaranteed write time and processes the host write request as a write-through host write request, wherein the host write request is not stored in the write cache, wherein the time to fill the stripe is the size of the stripe comprising the host write request divided by the data rate of a corresponding host write stream comprising the host write request.
20. The system of claim 19, wherein after the storage controller receives the host write request and before the storage controller calculates the time to fill the stripe comprising the host write request, the storage controller determines if the host write request fits into an existing host write stream comprising a set of LBA-sequential host write requests, wherein if the host write request does not fit into an existing host write stream, then the storage controller creates a new host write stream comprising:
a time stamp identifying the time the new host write stream is created; and
a current burst length equal to a host write request size,
wherein the corresponding host write stream is one of an existing host write stream and the new host write stream, wherein if the host write request fits into the corresponding host write stream, then the storage controller updates host write stream metadata for the host write request.