1. A method for determining how long a fuel cell system has not delivered hydrogen to an anode side of a fuel cell stack after a system shut-down, said method comprising:
determining whether the system has been shut-down;
incrementing a stand-by time if the system has been shut-down and a key is in a vehicle ignition;
incrementing a shut-off off time if the system has been shut-down and the key is out of the vehicle ignition;
determining whether the ignition has been turned on after a previous ignition off event;
adding the stand-by time and the shut-off time to provide an off-time that can be used to determine the gas constituency in the anode side of the stack; and
determining whether dilution air is being provided from a compressor to dilute anode exhaust.
2. The method according to claim 1 further comprising determining whether a fuel cell system battery has lost power when the ignition is off.
3. The method according to claim 2 further comprising setting the stand-by time to zero if the fuel cell system battery has lost power.
4. The method according to claim 1 further comprising setting the stand-by time to zero if the dilution air is being provided.
5. The method according to claim 1 wherein the fuel cell stack includes a first split stack and a second split stack that operate under anode flow-shifting.
6. The method according to claim 1 wherein the system shut-down includes sealing the cathode and anode side of the fuel cell stack.
7. The method according to claim 1 wherein the off-time is used to determine a proper start-up sequence of the fuel cell system.
8. A method for determining how long a fuel cell system in a vehicle has been shut-down, said method comprising:
incrementing a stand-by time if the system has been shut-down, but a key is in a vehicle ignition in an on or accessory position;
incrementing a shut-off off time if the system has been shut-down and the key is out of the vehicle ignition;
adding the stand-by time and the shut-off time to provide a total system off-time;
determining whether dilution air is being provided from a compressor to dilute anode exhaust; and
setting the stand-by time to zero if the dilution air is being provided.
9. The method according to claim 8 further comprising determining whether a fuel cell system battery has lost power when the ignition is off.
10. The method according to claim 9 further comprising setting the stand-by time to zero if the fuel cell system battery has lost power.
11. The method according to claim 8 wherein the fuel cell stack includes a first split stack and a second split stack that operate under anode flow-shifting.
12. The method according to claim 8 wherein the system shut-down includes sealing the cathode and anode side of the fuel cell stack.
13. The method according to claim 8 wherein the total system off-time is used to determine a proper start-up sequence of the fuel cell system.
14. A method for determining how long split fuel cell stacks in a fuel cell system on a vehicle have been shut-down, said method comprising:
incrementing a stand-by time if the split stacks have been shut-down, but a key is in a vehicle ignition and is in an on or accessory position;
incrementing a shut-off off time if the split stacks have been shut-down and the key is out of the vehicle ignition;
determining whether the ignition has been turned on after a previous ignition off event; and
adding the stand-by time and the shut-off time to provide an off-time that can be used to determine the gas constituency in the anode side of the stack and determine a proper start-up sequence of the fuel cell system.
15. The method according to claim 14 further comprising determining whether a fuel cell system battery has lost power when the ignition is off.
16. The method according to claim 15 further comprising setting the stand-by time to zero if the fuel cell system battery has lost power.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. An integrated circuit for high-resolution timing measurement, comprising:
a delay pulse generator;
a first oscillator to generate a first clock with a first frequency;
a second oscillator to generate a second clock with a second frequency;
an oscillator tuner;
a sampling module;
a counter;
wherein the delay pulse generator is configured to generate a delayed pulse from the second clock, the oscillator tuner is configured to control the second frequency to be as close as possible to the first frequency without being the same as the first frequency, the sampling module is configured to sample the delayed pulse at the first frequency, the counter is configured to generate a digital counter value by counting a number of samples made by the sampling module, and the digital counter is configured to output a count value indicating a time width of the delayed pulse.
2. The integrated circuit of claim 1, wherein the sampling module is a D flip-flop.
3. The integrated circuit of claim 1, wherein the counter has also statistical computational capabilities for measuring data multiple times.
4. The integrated circuit of claim 1, wherein the digital counter is configured to shift out a count value from the counter to an outside circuit for further processing.
5. The integrated circuit of claim 1, wherein the second oscillator is a tunable ring oscillator.
6. The integrated circuit of claim 5, wherein the second oscillator has one or more coarse tune stages and one or more fine tune stages wherein each coarse tune stage is configured to add a first time delay to the tunable ring oscillator that is longer than a second time delay that each fine tune stage is configured to add.
7. The integrated circuit of claim 6, wherein each coarse tune stage comprising:
a multiplexer; and
one or more inverters;
wherein a first input path of the coarse stage goes through the inverters to be connected to the multiplexer, a second input path to the coarse stage is connected directly to the multiplexer, and a control signal of the multiplexer can select one of the first input path and the second input path as an output.
8. The integrated circuit of claim 6, wherein each fine tune stage comprises:
a first input path including a first inverter and a CMOS pass transistor gate; and
a second input path including a second inverter;
wherein the first input path and the second input path are connected in parallel to an output of the fine tune stage and a control signal can turn on the first input path.
9. The integrated circuit of claim 6, wherein the second time delay multiplied by a number of the fine tune stages is approximately the same as the first time delay.
10. The integrated circuit of claim 1, further comprising a reset module that can send a reset signal to at least one of the sampling module and the counter.
11. The integrated circuit of claim 10, further comprising a reset counter that counts the reset signal sent to the counter.
12. An integrated circuit for high-resolution timing measurement, comprising:
a delay pulse generator;
a first oscillator to generate a first clock with a first frequency;
a second oscillator to generate a second clock with a second frequency;
an oscillator tuner;
a sampling module;
a counter;
wherein the delay pulse generator is configured to generate a delayed pulse from the second clock, the oscillator tuner is configured to control the second frequency to be as close as possible to the first frequency without being the same as the first frequency, the second oscillator is a tunable ring oscillator, the second oscillator has one or more coarse tune stages and one or more fine tune stages wherein each coarse tune stage is capable of adding a first time delay to the tunable ring oscillator that is longer than a second time delay that each fine tune stage is capable of adding, the sampling module is configured to sample the delayed pulse at the first frequency, the counter in configured to generate a digital counter value by counting a number of samples by the sampling module, and the digital counter is configured to output the a time width of the delayed pulse as the digital counter value.
13. The integrated circuit of claim 12, wherein the sampling module is a D flip-flop.
14. The integrated circuit of claim 12, wherein the counter has also statistical computational capabilities for measuring data multiple times.
15. The integrated circuit of claim 12, wherein each coarse tune stage comprising:
a multiplexer; and
one or more inverters;
wherein a first input path of the coarse stage goes through the inverters to be connected to the multiplexer, a second input path to the coarse stage is also connected directly to the multiplexer, and a control signal of the multiplexer is capable of selecting one of the first input path and the second input path as an output.
16. The integrated circuit of claim 12, wherein each fine tune stage comprising:
a first input path including a first inverter and a CMOS pass transistor gate; and
a second input path including a second inverter;
wherein the first input path and the second input path capable of being connected in parallel to an output of the fine tune stage and a control signal is capable of turning on the first input path.
17. The integrated circuit of claim 12, wherein the second time delay multiplied by a number of the fine tune stages is approximately the same as the first time delay.
18. An integrated circuit for high-resolution timing measurement, comprising:
a delay pulse generator;
a first oscillator to generate a first clock with a first frequency;
a second oscillator to generate a second clock with a second frequency;
an oscillator tuner;
a sampling module;
a counter; and
a reset module that can send a reset signal to the sampling module andor the counter;
wherein the delay pulse generator is configured to generate a delayed pulse from the second clock, the oscillator tuner in configured to control the second frequency to be as close as possible to the first frequency without being the same as the first frequency, the second oscillator is a tunable ring oscillator, the second oscillator has one or more coarse tune stages and one or more fine tune stages wherein each coarse tune stage is capable of adding a first time delay to the tunable ring oscillator that is longer than a second time delay that each fine tune stage is capable of adding, the sampling module is a D flip-flop and is configured to sample the delayed pulse at the first frequency, the counter is configured to generate a digital counter value by counting a number of samples by the sampling module, the counter has also statistical computational capabilities for measuring data multiple times, and the digital counter is configures to output a time width of the delayed pulse as the digital counter value.
19. The integrated circuit of claim 18, wherein each coarse tune stage comprises:
a multiplexer; and
one or more inverters;
wherein a first input path of the coarse stage goes through the inverters to be connected to the multiplexer, a second input path to the coarse stage is also connected directly to the multiplexer, and a control signal of the multiplexer is capable of selecting one of the first input path and the second input path as an output.
20. The integrated circuit of claim 18, wherein each fine tune stage comprising:
a first input path including a first inverter and a CMOS pass transistor gate; and
a second input path including a second inverter;
wherein the first input path and the second input path are connected in parallel to an output of the fine tune stage and a control signal is capable of turning on the first input path.