1. A method of fabrication of an interconnect opening for a semiconductor device; comprising the steps of:
forming a lower interconnect and an insulating layer over a semiconductor structure; a portion of said lower interconnect is exposed;
forming a first hardmask over said lower interconnect and said insulating layer;
forming a dielectric layer over said first hardmask layer;
forming a second hardmask over said dielectric layer;
etching an interconnect opening in said first hardmask, said dielectric layer and said second hardmask layer;
forming an interconnect in said interconnect opening.
2. The method of claim 1 wherein the first hardmask and said second hardmask are comprised of the same material.
3. A method of fabrication of an interconnect opening for a semiconductor device; comprising the steps of:
forming a lower interconnect and an insulating layer over a semiconductor structure;
forming a first hardmask over said lower interconnect and said insulating layer;
forming a dielectric layer over said first hardmask layer;
forming a second hardmask over said dielectric layer;
in a first etch step, etching a first interconnect opening in said first hardmask, said dielectric layer and said second hardmask layer; the dielectric layer in said first interconnect opening has sidewalls; the first hardmask has an first hardmask overhang and the second hardmask has a second hardmask overhang where said first hardmask overhang and said second hardmask overhang extend out past the sidewall of the dielectric layer;
in a second etch step, etching the first and second hardmask overhangs and the dielectric layer form a first overhang-less interconnect opening; the second etch step essentially removes said first and second hardmask overhangs;
forming an interconnect in said first overhang-less interconnect opening.
4. The method of claim 3 wherein in the first etch step, the etch has an etch selectivity from the dielectric layer to the first and second hardmasks between 1:1 and 2:1.
5. The method of claim 3 wherein in the second etch step, the etch has an etch selectivity between the dielectric layer and the first and second hardmasks between about 1:5 and 1:100.
6. The method of claim 3 which further in comprises:
the first etch forms a damaged dielectric liner on said sidewalls of the dielectric layer; said damaged dielectric liner is comprised of a nonstoichiometric oxide; the second etch removes said damaged dielectric liner.
7. The method of claims 3 wherein said first hardmask and said second hardmask are comprised of oxide doped oxide; a fluorine doped oxide or low-temperature oxide; and has a thickness between 500 and 1000 angstroms.
8. The method of claim 3 wherein said dielectric layer is comprised of a low K material or ultra low K material.
9. The method of claim 3 wherein said dielectric layer is comprised of: carbon doped oxide (SiCOH), carbon containing low K dielectric with a dielectric constant less than 3.0, spin on low-k dielectrics or CVD ultra-low-k dielectrics and has a thickness between 1500 and 3000 angstroms.
10. The method of claim 3 wherein said first hardmask and said second hardmask is comprised of oxide, doped oxide or low-temperature oxide;
said dielectric layer is comprised of a material selected from the group consisting of carbon doped oxide (SiCOH), carbon containing low K dielectric with a dielectric constant less than 3.0, spin on low-k dielectrics and CVD ultra-low-k.
11. The method of claim 3 wherein after the first etch step and before the second etch step, the first and second hardmask overhangs have a width between 3 and 15 nm; the first interconnect opening has a diameter between 60 nm and 140 nm;
and after the second etch step, the first and second hardmask overhangs have a width between 0 and 30 angstroms.
12. The method of claim 3 wherein the first etch step comprises: a Carbon-fluorine chemistry, a temperature between 20 and 100 degree C.; a pressure between 20 and 100 mTorr, a Radio-frequency power<1000 w, with N2, H2, CO orand Ar additives;
the first etch step has an etch selectivity between 1:1 to 2:1 of the dielectric layer to the first & second hardmasks.
13. The method of claim 3 wherein the second etch comprise a wet dilute HF etch with a etch selectivity between the hardmask and the dielectric layer between 1:1 and 2:1.
14. The method of claim 3 wherein said first and said second hardmask are comprised of essentially the same material.
15. A method of fabrication of an interconnect opening for a semiconductor device; comprising the steps of:
a) forming a lower interconnect and insulating layer over a semiconductor structure;
b) forming a first hardmask over said lower interconnect and insulating layer;
(1) said first hardmask is comprised of a material selected from the group consisting of: oxide, doped oxide or low-temperature oxide;
c) forming a dielectric layer over said first hardmask layer;
(1) said dielectric layer is comprised of a material selected from the group consisting of: SiCOH, carbon containing low K dielectric, spin on low-k dielectrics, porous silica glass, organo silica glass, aromatic hydrocarbon materials, and CVD ultra-low-k dielectric;
d) forming a second hardmask over said dielectric layer;
(1) said second hardmask is comprised of a material selected from the group consisting of: oxide, doped oxide or low-temperature oxide;
e) in a first etch step, etching a first interconnect opening in said first hardmask, dielectric layer and said second hardmask layer; the first hardmask has an first hardmask overhang and the second hardmask has a second hardmask overhang where the first and second hardmask overhangs extend out past the sidewall of the dielectric layer;
the first etch forms a damaged dielectric layer from the dielectric layer lining the first interconnect opening;
(1) the first etch step comprises: using a carbon-fluorine chemistry; the first etch step has an etch selectivity between 1:1 to 2:1 of the dielectric layer to said first hardmask and said second hardmask;
f) in a second etch step, etching damaged dielectric layer and the overhangs of the hardmask layers to remove said first and second hardmask overhangs and form a first overhang-less interconnect opening and cleaning said first overhand-less interconnect opening;
(1) the second etch comprises an etch with an etch selectivity between the damaged dielectric layer and the hardmask between 1:1 and 2:1;
g) forming an interconnect in said first overhang-less interconnect opening.
16. The method of claim 15 wherein in the second etch step, the etch has an etch selectivity between the dielectric layer and said first hardmask and said second hardmask between about 1:5 and 1:100.
17. The method of claim 15 wherein in the first etch step, the first etch step comprises: using a carbon-fluorine chemistry, at a temperature between 20 and 100 degree C.; at a pressure between 10 and 100 mTorr, at a radio-frequency power<1000 w, with N2, H2, CO orand Ar additives.
18. The method of claim 15 wherein the second etch comprise a wet dilute HF etch or a dry etch.
19. The method of claim 15 wherein said first and said second hardmask are comprised of essentially the same material.
20. The method of claim 15 wherein said insulating layer is an interlevel dielectric layer and said lower interconnect is a contact to a substrate.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A resin composition comprising a poly lactic acid resin comprising
an L-lactic acid block and a D-lactic acid block, which blocks are bonded by carbonate bonding; and
a compound having flame retardancy kneaded with the L-lactic acid block and the D-lactic acid block, which blocks are bonded by carbonate bonding, wherein
the compound having flame retardancy is a compound that exhibits no flame retardancy by itself, but exhibits flame a retardancy of HB or higher as defined by UL-94 when the compound is added to a resin composition that has a flame retardancy of lower than HB as defined by UL-94.
2. The resin composition according to claim 1, wherein an average composition ratio by weight of the L-lactic acid block to the D-lactic acid block is from about 15:85 to about 85:15.
3. The resin composition according to claim 1, wherein the resin composition further contains at least one resin selected from the group consisting of a poly lactic acid resin, a polycarbonate resin, a polypropylene resin, a polyester resin, and a polyamide resin.
4. The resin composition according to claim 1, wherein a crystallization rate of the resin composition is from about 15 sec to about 60 sec.
5. A resin molding comprising
a poly lactic acid resin comprising an L-lactic acid block and a D-lactic acid block, which blocks are bonded by carbonate bonding; and
a compound having flame retardancy kneaded with the L-lactic acid block and the D-lactic acid block, which blocks are bonded by carbonate bonding, wherein
the compound having flame retardancy is a compound that exhibits no flame retardancy by itself, but exhibits flame a retardancy of HB or higher as defined by UL-94 when the compound is added to a resin composition that has a flame retardancy of lower than HB as defined by UL-94.
6. The resin molding according to claim 5, wherein an average composition ratio by weight of the L-lactic acid block to the D-lactic acid block is from about 15:85 to about 85:15.
7. The resin molding according to claim 5, wherein the resin molding further contains at least one resin selected from the group consisting of a poly lactic acid resin, a polycarbonate resin, a polypropylene resin, a polyester resin, and a polyamide resin.
8. The resin molding according to claim 5, wherein a crystallization rate of the resin molding is from about 15 sec to about 60 sec.
9. The resin molding according to claim 5, wherein a component of an electronic or electric instrument comprises the resin molding.
10. The resin composition according to claim 1, wherein the compound having flame retardancy is a member selected from the group consisting of a phosphorus-based flame retardant, a silicone-based flame retardant, a nitrogen-containing flame retardant, a sulfuric acid-based flame retardant, and an inorganic hydroxide-based flame retardant.
11. The resin composition according to claim 1, wherein the compound having flame retardancy is a member selected from the group consisting of melamine phosphate, ammonium phosphate, aluminum phosphate, dimethyl siloxane, nano silica, silicone-modified polycarbonate, a melamine compound, a triazine compound, melamine sulfate, guanidine sulfate, magnesium hydroxide, and aluminum hydroxide.
12. The resin molding according to claim 5, wherein the compound having flame retardancy is a member selected from the group consisting of a phosphorus-based flame retardant, a silicone-based flame retardant, a nitrogen-containing flame retardant, a sulfuric acid-based flame retardant, and an inorganic hydroxide-based flame retardant.
13. The resin molding according to claim 5, wherein the compound having flame retardancy is a member selected from the group consisting of melamine phosphate, ammonium phosphate, aluminum phosphate, dimethyl siloxane, nano silica, silicone-modified polycarbonate, a melamine compound, a triazine compound, melamine sulfate, guanidine sulfate, magnesium hydroxide, and aluminum hydroxide.