What is claimed is:
1. A method for generating bit reliabilities by means of a simplified Soft Output Viterbi Algorithm, the method on a processing unit for fault-tolerant communication comprising the steps of:
receiving a sequence of numbers r over a channel, having a channel impulse response h with coefficients h0, h1, . . . , hv, wherein v1 is a length of the response;
detecting by means of a Viterbi detector candidate symbols xx1 . . . xk from the received sequence of numbers r; and
generating symbol reliability estimates for each symbol position from r and for each detected candidate symbol x using error filters.
2. The method as defined in claim 1, wherein the error filters are used to provide reliability estimates relative to error events for predetermined common error patterns that are most likely causes of errors.
3. The method as defined in claim 1, further comprising the steps of:
convolving an error sequence with hR, a time reversal of h; and
passing the convolution (*hR) through a bank of error filters with taps determined by the error events ei.
4. The method as defined in claim 3, wherein the step of passing the convolution through the error filter is given by:
(*hR)sk(e).
5. The method as defined in claim 4, further comprising the step of:
computing (k, e) margins mk,e by summing an energy term f2 with a result of the convolution through the error filter wherein the result of the convolution is multiplied by a constant factor of 2 before being summed with the constant energy term.
6. The method as defined in claim 5, further comprising the step of:
testing error events for plausibility in a plurality of qualification modules wherein only plausible error events that are binary sequences resulting in a different detected decision are considered for bit reliability determination i.e., for the j-th bit position Viterbi margins are computed only over those j-qualified pairs (k, e) that qualify under the following two conditions:
Q1: for ikIv1, . . . , kv
if (sk(e))I, then xi0 and
if (sk(e))I, then xI1
Q2: (sk(e))J0.
7. The method as defined in claim 6, further comprising the steps of:
buffering mk,e that are j-qualified; and
combining such mk,e to produce a reliability for the jth bit position.
8. The method as defined in claim 7, wherein the combining step is a minimization followed by multiplication by an appropriate sign.
9. The method as defined in claim 7, wherein the combining step is an averaging followed by multiplication by an appropriate sign.
10. A computer readable medium comprising instructions for generating bit reliabilities by means of a simplified Soft Output Viterbi Algorithm, the instructions for fault-tolerant communication to and from a processing unit comprising the instructions of:
receiving a sequence of numbers r over a channel, having a channel impulse response h with coefficients h0, h1, . . . , hv, wherein v1 is a length of the response;
detecting by means of a Viterbi detector candidate symbols xx1 . . . xk from the received sequence of numbers r; and
generating symbol reliability estimates for each symbol position from r and for each detected candidate symbol x using error filters.
11. The computer readable medium as defined in claim 10, wherein the error filters are used to provide reliability estimates relative to error events for predetermined common error patterns that are most likely causes of errors.
12. The computer readable medium as defined in claim 10, further comprising the instructions of:
convolving an error sequence with hR, a time reversal of h; and
passing the convolution (*hR) through a bank of error filters with taps determined by the error events ei.
13. The computer readable medium as defined in claim 12, wherein the instruction of passing the convolution through the error filter is given by:
(*hR)sk(e).
14. The computer readable medium as defined in claim 13, further comprising the instruction of:
computing (k,e) margins mk,e by summing an energy term f2 with a result of the convolution through the error filter wherein the result of the convolution is multiplied by a constant factor of 2 before being summed with the constant energy term.
15. The computer readable medium as defined in claim 14, further comprising the instruction of:
testing error events for plausibility in a plurality of qualification modules wherein only plausible error events that are binary sequences resulting in a different detected decision are considered for bit reliability determination i.e., for the j-th bit position Viterbi margins are computed only over those j-qualified pairs (k,e) that qualify under the following two conditions:
Q1: for ikIv1, . . . , kv
if (sk(e))I, then xi0 and
if (sk(e))I, then xI1
Q2: (sk(e))J0.
16. The computer readable medium as defined in claim 15, further comprising the instructions of:
buffering mk,e that are j-qualified; and
combining such mk,e to produce a reliability for the jth bit position.
17. The computer readable medium as defined in claim 16, wherein the combining instruction is a minimization followed by multiplication by an appropriate sign.
18. The computer readable medium as defined in claim 16, wherein the combining instruction is an averaging followed by multiplication by an appropriate sign.
19. A system for generating bit reliabilities by means of a simplified Soft Output Viterbi Algorithm, the system for fault-tolerant communication to and from a processing unit comprising:
an equalizer for receiving a sequence of numbers that the equalizer identifies as r over a channel, having a channel impulse response h with coefficients h0, h1, . . . , hv, wherein v1 is a length of the response;
a viterbi detector for detecting candidate symbols xx1 . . . xk from the received sequence of numbers r; and
a qualification and minimization module for generating symbol reliability estimates for each symbol position from r and for each detected candidate symbol x using error a filters.
20. The system as defined in claim 19, wherein the error filters are used to provide reliability estimates relative to error events for predetermined common error patterns that are most likely causes of errors.
21. The system as defined in claim 19, further comprising:
a filter for convolving an error sequence with hR , a time reversal of h; and
a bank of error filters with taps determined by the error events ei for receiving and passing the convolution (*hR) there through.
22. The system as defined in claim 21, wherein passing the convolution through the error filter is given by:
(*hR)sk(e).
23. The system as defined in claim 22, further comprising:
a summation unit for computing (k,e) margins mk,e by summing an energy term f2 with a result of the convolution through the error filter wherein the result of the convolution is multiplied by a constant factor of 2 before being summed with the constant energy term.
24. The system as defined in claim 23, further comprising:
a plurality of qualification modules for testing error events for plausibility wherein only plausible error events that are binary sequences resulting in a different detected decision are considered for bit reliability determination i.e., for the j-th bit position Viterbi margins are computed only over those j-qualified pairs (k, e) that qualify under the following two conditions:
Q1: for ikIv1, . . . , kv
if (sk(e))I, then xi0 and
if (sk(e))I, then xI1
Q2: (sk(e))J0.
25. The system as defined in claim 24, further comprising:
accumulated minimum margin buffers for buffering mk,e that are j-qualified; and
a combining unit for combining such mk,e to produce a reliability for the jth bit position.
26. The system as defined in claim 25, wherein the combining unit comprises a combining unit that performs a minimization followed by multiplication by an appropriate sign.
27. The system as defined in claim 25, wherein the combining operation comprises a combining unit that performs an averaging followed by multiplication by an appropriate sign.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A transceiver, comprising:
a processing module operably coupled to generate outbound non-amplitude modulated symbols from first outbound data, to generate outbound amplitude modulated symbols from second outbound data, to generate first inbound data from inbound non-amplitude modulated symbols, and to generate second inbound data from inbound amplitude modulated symbols;
a combiner operably coupled to modulate the amplitude modulated symbols onto a signal carrying the non-amplitude modulated symbols to produce a combined outbound RF signal;
a power amplifier module operably coupled to amplify the combined outbound RF signal;
a low noise amplifier module operably coupled to amplify a combined inbound RF signal to produce an amplified combined inbound RF signal; and
a splitter operably coupled to convert the amplified combined inbound RF signal into inbound non-amplitude modulated symbols and into inbound amplitude modulated symbols.
2. The transceiver of claim 1, wherein said processing module includes a radio frequency identification (RFID) baseband processing module operable generate the outbound amplitude modulated symbols and a transceiver baseband processing module operable generate the outbound non-amplitude modulated symbols.
3. The transceiver of claim 2, further comprising:
an RFID RF front end operably coupled to convert the outbound amplitude modulated symbols into an outbound amplitude modulated RF signal; and
a transceiver RF front end operably coupled to convert the outbound non-amplitude modulated symbols into an outbound non-amplitude modulated RF signal.
4. The transceiver of claim 3, wherein said combiner is operable to combine the outbound amplitude modulated RF signal with the outbound non-amplitude modulated RF to produce the combined outbound RF signal.
5. The transceiver of claim 3, wherein said power amplifier includes said combiner, said power amplifier being further operable to modulate the outbound amplitude modulated RF signal on the outbound non-amplitude modulated RF signal to produce the combined outbound RF signal.
6. The transceiver of claim 3, wherein said RFID RF front end includes at least a portion of said splitter, said RFID RF front end being further operably coupled to convert the amplified combined inbound RF signal into an inbound amplitude modulated near baseband signal.
7. The transceiver of claim 3, wherein said transceiver RF front end includes at least a portion of said splitter, said transceiver RF front end being further operably coupled to convert the amplified combined inbound RF signal into an inbound non-amplitude modulated near baseband signal.
8. The transceiver of claim 3, wherein said splitter is operably coupled to split the combined inbound RF signal into an inbound amplitude modulated RF signal and an inbound non-amplitude modulated RF signal.
9. The transceiver of claim 8, wherein said RFID RF front end is further operable to convert the inbound amplitude modulated RF signal into an inbound amplitude modulated near baseband signal and to provide the inbound amplitude modulated near baseband signal to said RFID baseband processing module.
10. The transceiver of claim 9, wherein said transceiver RF front end is further operable to convert the inbound non-amplitude modulated RF signal into an inbound non-amplitude modulated near baseband signal and to provide the inbound non-amplitude modulated near baseband signal to said transceiver baseband processing module.
11. The transceiver of claim 10, wherein said RFID baseband processing module and said transceiver baseband processing module are integrated.
12. The transceiver of claim 2, wherein said RFID baseband processing module is operable to generate an outbound amplitude-modulated digital signal carrying the outbound amplitude modulated symbols and said transceiver baseband processing module is operable to generate an outbound non-amplitude modulated digital signal carrying the outbound non-amplitude modulated symbols.
13. The transceiver of claim 12, wherein said combiner is operable to combine the outbound amplitude-modulated digital signal with the outbound non-amplitude modulated digital signal to produce a combined outbound digital signal.
14. The transceiver of claim 13, further comprising:
a digital-to-analog converter operably coupled to convert the combined outbound digital signal into a combined outbound near baseband signal.
15. The transceiver of claim 12, further comprising:
a first digital-to-analog converter operably coupled to convert the outbound amplitude modulated digital signal into an outbound amplitude modulated near baseband signal; and
a second digital-to-analog converter operably coupled to convert the outbound non-amplitude modulated digital signal into an outbound non-amplitude modulated near baseband signal, and wherein said combiner is operable to combine the outbound non-amplitude modulated near baseband signal with the outbound amplitude modulated near baseband signal to produce a combined outbound near baseband signal.
16. The transceiver of claim 12, further comprising:
an up-conversion module operable to convert the combined outbound near baseband signal to the combined outbound RF signal.
17. The transceiver of claim 16, further comprising:
a down-conversion module operable to convert the amplified combined inbound RF signal into a combined inbound near baseband signal.
18. The transceiver of claim 17, wherein said splitter is operable to split the combined inbound near baseband signal into an inbound amplitude-modulated near baseband signal and an inbound non-amplitude modulated near baseband signal.
19. The transceiver of claim 18, further comprising:
a first digitization module operably coupled to convert the inbound non-amplitude modulated near baseband signal into an inbound non-amplitude modulated digital signal and to provide the inbound non-amplitude modulated digital signal to said transceiver baseband processing module; and
a second digitization module operably coupled to convert the inbound amplitude modulated near baseband signal into an inbound amplitude modulated digital signal and to provide the inbound amplitude modulated digital signal to said RFID baseband processing module.
20. The transceiver of claim 18, further comprising:
a digitization module operably coupled to convert the combined inbound near baseband signal into a combined inbound digital signal, and wherein said combiner is operably coupled to split said combined inbound digital signal into an inbound amplitude modulated digital signal for providing to said RFID baseband processing module and an inbound non-amplitude modulated digital signal for providing to said transceiver baseband processing module.
21. A method for simultaneously operating a wireless communication device in a transceiver mode and a radio frequency identification (RFID) mode, comprising the steps of:
generating outbound non-amplitude modulated symbols from first outbound data;
generating outbound amplitude modulated symbols from second outbound data;
modulating the amplitude modulated symbols onto a signal carrying the non-amplitude modulated symbols to produce a combined outbound RF signal;
receiving a combined inbound RF signal; and
converting the combined inbound RF signal into inbound non-amplitude modulated symbols and into inbound amplitude modulated symbols.