1. An integrated circuit, comprising:
a semiconductor substrate that has a well region containing a first conductivity type impurity; and
an enhancement type MOS transistor and a plurality of depletion type MOS transistors, each of which is formed in the well region and has a channel region under a gate electrode,
wherein at least one of the depletion type MOS transistors has, in the channel region, an implantation region into which a second conductivity type impurity is implanted so that a threshold voltage is adjusted,
the implantation region has the first conductivity type impurity and the second conductivity type impurity, and
the second conductivity type impurity has a concentration that is higher than a concentration of the first conductivity type impurity.
2. The integrated circuit according to claim 1,
wherein a first conductivity type pocket implantation region is provided in the channel region, which is formed under the implantation region, and
the second conductivity type impurity is implanted to a depth shallower than a depth at which the pocket implantation region is formed.
3. The integrated circuit according to claim 1,
wherein the plurality of depletion type MOS transistors include a depletion type MOS transistor different from others in threshold voltage.
4. A solid-state imaging device comprising an integrated circuit as claimed in claim 1.
5. The integrated circuit according to claim 2,
wherein the second conductivity type impurity implanted into the channel region is phosphorus.
6. The integrated circuit according to claim 2,
wherein the second conductivity type impurity implanted into the channel region is arsenic.
7. An integrated circuit, comprising:
a semiconductor substrate that has a well region containing a first conductivity type impurity; and
an enhancement type MOS transistor and a plurality of depletion type MOS transistors, each of which is formed in the well region and has a channel region under a gate electrode,
wherein at least one of the depletion type MOS transistors has, in the channel region:
an implantation region into which a second conductivity type impurity is implanted so that a threshold voltage is adjusted; and
a first conductivity type pocket implantation region formed under the implantation region,
the implantation region has a concentration of the second conductivity type impurity that is higher than a concentration of the first conductivity type impurity, and
the second conductivity type impurity is implanted to a depth shallower than a depth at which the pocket implantation region is formed.
8. The integrated circuit according to claim 7,
wherein the first conductivity type impurity is boron and the second conductivity type impurity is arsenic.
9. The integrated circuit according to claim 7,
wherein the plurality of depletion type MOS transistors include a depletion type MOS transistor different from others in threshold voltage.
10. A solid-state imaging device comprising an integrated circuit as claimed in claim 7.
11. A method of manufacturing an integrated circuit, the integrated circuit comprising an enhancement type MOS transistor and a plurality of depletion type MOS transistors that are formed on a semiconductor substrate having a well region containing a first conductivity type impurity, the method comprising, with respect to at least one of the depletion type MOS transistors:
implanting a second conductivity type impurity into the well region so as to form a second conductivity type implantation region;
forming a gate electrode on the implantation region; and
implanting, using the gate electrode as a mask, a second conductivity type impurity into the semiconductor substrate so as to form drain and source regions.
12. The method according to claim 11,
wherein, after the gate electrode is formed, using the gate electrode as a mask, a first conductivity type impurity is implanted under the implantation region so that a pocket region is formed.
13. A method of manufacturing a solid-state imaging device,
wherein a method of manufacturing an integrated circuit as claimed in claim 11 is used.
14. A method of manufacturing an integrated circuit, the integrated circuit comprising an enhancement type MOS transistor and a plurality of depletion type MOS transistors that are formed on a semiconductor substrate having a well region containing a first conductivity type impurity, the method comprising, with respect to at least one of the depletion type MOS transistors:
implanting a first conductivity type impurity into the well region;
implanting a second conductivity type impurity heavier than the first conductivity type impurity into the well region into which the first conductivity type impurity has been implanted so as to form a second conductivity type implantation region;
forming a gate electrode on a portion of the implantation region;
implanting, using the gate electrode as a mask, a first conductivity type impurity under the implantation region so as to form a pocket region; and
implanting, using the gate electrode as a mask, a second conductivity type impurity into a portion of the implantation region on which the gate electrode is not formed so as to form drain and source regions.
15. A method of manufacturing a solid-state imaging device,
wherein a method of manufacturing an integrated circuit as claimed in claim 14 is used.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A method of manufacturing improved cast anodes for corrosion protection in storage tanks, comprising the steps of:
integrating a plurality of spaced steel core rods within a sheet of cast galvanic anode material;
dividing the galvanic anode material into segments such that a width of each segment is at least four times as great as a thickness of the galvanic anode material.
2. The method of claim 1 including the additional step of:
incorporating a plurality of spaced detents within the cast sheet for ease of separating the sheet into multiple segments.
3. The method of claim 1 including the step of:
forming each segment to be about 4 to 8 times wider than thick.
4. The method of claim 1 including the step of:
forming each segment to have a length that is at least 6 times the width.
5. The method of claim 4 including the step of:
forming each segment to have a length that is about 2-18 times the width.
6. The method of claim 1 wherein the thickness of the cast anode segment is less than about 1 inch.
7. The method of claim 6 therein the thickness of the cast anode is about \u215b inch to less than about 1 inch.
8. The method of claim 7 wherein the thickness of the cast anode is about \u215b inch to about 0.375 inch.
9. The method of claim 1 wherein the segments include at least one steel core rod therein.
10. The method of claim 1 wherein the segments include multiple steel core rods therein.
11. An improved anode for storage tanks, comprising:
a sacrificial cast galvanic anode having a width that is approximately at least four times its thickness;
a galvanized steel core rod in contact therewith.
12. The anode of claim 11 wherein the galvanic anode is comprised of zinc.
13. The anode of claim 11 wherein the galvanic anode is comprised of magnesium.
14. The anode of claim 11 wherein the galvanic anode is comprised of aluminum.
15. The anode of claim 11 wherein the thickness of the galvanic anode is approximately \u215b inch to less than 1 inch.
16. The anode of claim 15 wherein the thickness of the galvanic anode is approximately \u215b inch to about 0.375 inch.
17. The anode of claim 11 wherein a length of each anode is about 2-18 times the thickness.
18. The anode of claim 11 wherein the width of each anode is about 4-8 times the thickness.
19. A method of reducing corrosion in a storage tank, comprising the steps of:
integrating a plurality of spaced steel cores within a galvanic anode material;
dividing the galvanic anode material into segments such that a width of each segment is at least four times as great as a thickness of the galvanic anode material;
placing at least one segment of the integrated steel core and galvanic anode in a tank in a position prone to corrosion;
reducing the incidence of corrosion within said tank.
20. The method of claim 19 wherein the at least one segment of integrated steel core and galvanic anode is submerged in accumulated water within a storage tank.
21. The method of claim 19 including the additional step:
sacrificing the anode material to prevent corrosion in the tank.
22. The method of claim 20 wherein substantially all surfaces of the anode material direct corrosion control.
23. The method of claim 19 including the additional stop of dividing the galvanic anode material into segments wherein each segment is about 4 to 8 times wider than it is thick, and 6 to 18 times longer than the width.