1. A configurable integrated circuit (IC) having:
a plurality of wiring layers;
a first via programmed interconnect circuit having a first set of input terminals and a set of output terminals, wherein the interconnect circuit has several connection schemes for connecting the first input set to the output set; the first via programmed interconnect circuit operating equivalently to a second configurable interconnect circuit that performs different interconnect operations based on different configuration data sets;
a second set of input terminals for carrying a set of input signals, wherein a plurality of input terminals in the first set are on a different wiring layer of the IC than a plurality of input terminals in the second set; and
a plurality of vias each for connecting an input terminal in the first set with an input terminal in the second set;
wherein during the design of the IC, the plurality of vias are selected from a group of potential vias between the first and second set of input terminals, said selection resulting in the first via programmed interconnect circuit implementing the equivalent operation of the second configurable interconnect circuit when the second configurable interconnect circuit receives a particular configuration data set;
wherein the interconnect circuit receives a control signal and based on this control signal connects the first input terminal set to the output set by using a particular one of the connection schemes.
2. The integrated circuit of claim 1 further comprising a signal generator that generates the control signal.
3. The integrated circuit of claim 1, wherein all input terminals in the first and second sets overlap at the same angle.
4. The integrated circuit of claim 3, wherein the angle is 90\xb0.
5. The integrated circuit of claim 3, wherein all input terminals in the first set are on a different wiring layer than all input terminals in the second set.
6. The integrated circuit of claim 1, wherein the interconnect circuit is a decoder.
7. The integrated circuit of claim 1, wherein the interconnect circuit is a multiplexer.
8. The integrated circuit of claim 1, wherein the first via programmed interconnect circuit is one of a plurality of via programmed interconnect circuits of the IC, wherein the plurality of via programmed interconnect circuits are arranged in an array having multiple rows and columns, wherein each particular via programmed interconnect circuit in the set has:
a first set of input terminals and a set of output terminals, wherein the particular interconnect circuit has several connection schemes for connecting the first input set to the output set;
wherein the particular via programmed interconnect circuit operating equivalently to another configurable interconnect circuit that performs different interconnect operations based on different configuration data sets;
a second set of input terminals for carrying a set of input signals, wherein a plurality of input terminals in the first set are on a different wiring layer of the IC than a plurality of input terminals in the second set; and
a plurality of vias each for connecting an input terminal in the first set with an input terminal in the second set;
wherein during the design of the IC the plurality of vias are selected from a group of potential vias between the first and second set of input terminals, said selection resulting in the particular via programmed interconnect circuit implementing the equivalent operation of the other configurable interconnect circuit when the second configurable interconnect circuit receives a particular configuration data set;
wherein the particular interconnect circuit receives a control signal and based on this control signal connects the first input terminal set to the output set by using a particular one of the connection schemes.
9. The integrated circuit of claim 1 further comprising a set of logic circuits configurably connected by the interconnect circuits, wherein each logic circuit is for performing a set of functions.
10. A configurable integrated circuit (IC) having a plurality of wiring layers, said IC comprising:
a) a first via programmed interconnect circuit for connecting an input data set to an output data set, said first via programmed interconnect circuit having a first set of inputs, the first via programmed interconnect circuit operating equivalently to a second configurable interconnect circuit that performs different interconnect operations based on different configuration data sets;
b) a second set of inputs for providing the input data set, wherein a plurality of input terminals in the first set are on a different wiring layer of the IC than a plurality of input terminals in the second set;
c) a plurality of vias defined between certain inputs in the first set and certain inputs in the second set, wherein during the design of the IC, the plurality of vias are selected from a group of potential vias between the first and second set of input terminals, said selection resulting in the first via programmed interconnect circuit implementing the equivalent operation of the second configurable interconnect circuit when the second configurable interconnect circuit receives a particular configuration data set, and
d) a signal generator for supplying a control signal to the first via programmed interconnect circuit, which then connects the input data set to the output data set in a particular manner.
11. The integrated circuit of claim 10, wherein all inputs in the first and second sets overlap at the same angle.
12. The integrated circuit of claim 11, wherein the angle is 90\xb0.
13. The integrated circuit of claim 11, wherein all inputs in the first set are on a different wiring layer than all inputs in the second set.
14. A method of specifying a first via programmed interconnect circuit in a integrated circuit with a plurality of wiring layers, the first via programmed interconnect circuit operating equivalently to a second configurable interconnect circuit that performs different interconnect operations based on different configuration data sets, the method comprising:
a) defining a first set of input terminals and a set of output terminals for the first via programmed interconnect circuit;
b) defining a second set of input terminals for carrying a set of input signals, wherein at least a plurality of the second set of input terminals are on a different wiring layer than at least a plurality of the first set of input terminals;
c) from a group of potential vias between the first and second set of input terminals, defining a plurality of vias between certain input terminals in the first and second sets, such that the first via programmed interconnect circuit implements the equivalent operation of the second configurable interconnect circuit when the second configurable interconnect circuit receives a particular configuration data set; and
d) supplying a control signal to the first via programmed interconnect circuit to enable the first via programmed interconnect circuit to connect the first input terminal set to the output terminal set by using a particular one of a plurality of connection schemes that the first via programmed interconnect circuit can use to connect the first input terminal set to the output terminal set.
15. The method of claim 14 further comprising defining the set of potential via sites between the first input terminal set and the second input terminal set, wherein defining the set of vias comprises selecting certain potential via sites to place vias in order to embed configuration data in the set of vias.
16. The method of claim 15, wherein the potential via sites are arranged as a two-dimensional array of potential sites.
17. The method circuit of claim 14, wherein all inputs in the first and second sets of inputs overlap at the same angle.
18. The method of claim 17, wherein the angle is 90\xb0.
19. The method of claim 17, wherein all inputs in the first set are on a different wiring layer than all inputs in the second set.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A charge pump system, comprising:
a charge pump circuit, connected to receive a control signal and in response thereto, provide an output voltage at an output node; and
regulation circuitry responsive a multi-bit digital value, including:
a first comparator, having as output the control signal, a first input connected to receive a first reference voltage, and a second input connected to a first node;
a first current branch connected between the output node and ground, comprising:
a first variable resistance connected between the output node and the first node, the value of the first variable resistance is determined by a first set of bits of the digital value;
a first fixed resistance connected between the first node and ground;
a second current branch connected between the output node and ground in parallel with the first current branch, the second current branch comprising:
a second variable resistance connected between the output node and ground, including a fixed portion and an adjustable portion having a value determined by a second set of bits of the digital value, the bits of the second set being of lesser significance than the bits of the first set of bits in the digital value; and
a unity gain op-amp section, including:
a first transistor connected between the output node and the second variable resistance; and
a second comparator having an output connected to the control gate of the first transistor, a first input connected to receive a second reference voltage, and a second input connected to a node between the first transistor and the second variable resistance.
2. The charge pump system of claim 1, where the digital value is of N bits with the bits of the first set being the M most significant bits of the digital value and the second set being the (N\u2212M) least significant bits of the digital value, where M and N are positive integers, N being greater than M.
3. The charge pump system of claim 1, wherein the second variable resistance comprises:
N resistances selectively connectable between the output node and ground in parallel with a second fixed resistance in response to the N least significant bits of the digital value.
4. The charge pump system of claim 1, wherein the first and second reference voltages are of the same value.
5. The charge pump system of claim 1, wherein the second current branch further comprises:
a second transistor connected as a high-voltage protection element in series with the first transistor between the output node and the first transistor.
6. The charge pump system of claim 1, wherein the first current branch further comprises:
an offset resistance selectively connectable between the output node and the first node in series with the first variable resistance.
7. The charge pump system of claim 1, wherein the regulation circuitry further comprising:
a second fixed resistance, wherein the first and second current branches are both connected to the output node through the second fixed resistance.