What is claimed is:
1. A method of producing a metal-matrix composite coating on a surface of a substrate comprising:
a) melting a portion of said surface of said substrate with a heat source forming a melt pool;
b) feeding a reinforced metal matrix precursor into a melt zone so that molten precursor drops enter said melt pool;
c) allowing said molten precursor and melted substrate to mix, react and mix and react in said melt pool;
d) solidifying said pool forming a compound that coats said portion of said surface of said substrate; and
e) repeatedly redirecting said heat source to another portion of said surface and repeating steps a-d until a desired portion of the substrate surface is coated.
2. The method of claim 1 wherein said heat source comprises a concentrated spot source and said reinforced metal matrix precursor comprises a fiber-reinforced metal matrix precursor.
3. The method of claim 2 wherein said fiber-reinforced metal matrix precursor comprises fiber-reinforced metal matrix wire, fiber-reinforced metal matrix sheet, or fiber-reinforced metal matrix rod.
4. The method of claim 1 wherein said heat source comprises a concentrated spot source and said reinforced metal matrix precursor comprises a particle-reinforced metal matrix precursor.
5. The method of claim 4 wherein said particle-reinforced metal matrix precursor comprises a particle-reinforced metal matrix wire, particle-reinforced metal matrix sheet, or particle-reinforced metal matrix in a bulk form.
6. The method of claim 1 wherein said heat source comprises a concentrated line source and said reinforced metal matrix precursor comprises a fiber-reinforced metal matrix precursor.
7. The method of claim 6 wherein said fiber-reinforced metal matrix precursor comprises fiber-reinforced metal matrix wire, a plurality of fiber-reinforced metal matrix wires, fiber-reinforced metal matrix sheet, fiber-reinforced metal matrix mesh or fiber-reinforced metal matrix material in bulk form.
8. The method of claim 1 wherein said heat source is redirected by robot programmed to heat each portion of the surface.
9. The method of claim 1 wherein said heat source is redirected by raster-scanning a beam.
10. The method of claim 1 wherein said heat source comprises a distributed source and said precursor comprises a contoured sheet precursor.
11. The method of claim 10 wherein said contoured sheet precursor comprises a mesh sheet.
12. A method of producing a coating on a surface of a substrate comprising:
laying a precursor in a stationary manner on a surface of said substrate;
sweeping a path along said substrate surface with a heat source, locally melting the precursor at each successive location;
allowing reactive mixing, inert mixing and reactive and insert mixing of the melted precursor components; and
forming an intermetallic compound on said surface of said substrate as said melted material solidifies.
13. The method of claim 12 wherein a portion of the substrate is melted during the sweeping step and said reactive mixing, inert mixing and reactive and insert mixing are allowed among the precursor components and said melted substrate.
14. The method of claim 12 wherein said precursor comprises a plurality of materials formed into a sheet.
15. The method of claim 14 wherein a said sheet comprises a mesh sheet.
16. The method of claim 12 wherein said precursor is fixed to said substrate surface by bonding, mechanically fixing or joining.
17. The method of claim 12 wherein said heat source comprises a concentrated heat source.
18. The method of claim 12 wherein said precursor comprises a plurality of metallic layers deposited on said substrate surface, the plurality of metallic layers plated or sprayed on said substrate surface.
19. The method of claim 18 further comprising ceramic particulates co-deposited with said plurality of metallic layers.
20. The method of claim 19 wherein said ceramic particulates are alumina, silicon carbide or mullite.
21. A composite coated product formed by the process of claim 1.
22. A coating on a surface of a substrate formed by the process of claim 12.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A method of operating non-volatile storage having a plurality of NAND strings each having a plurality of non-volatile storage elements above a channel, a first select transistor at a first end of the NAND string, and a second select transistor at a second end of the NAND string, the first and second select transistors each having a diffusion region on the opposite side of the select transistor from the channel region, the method comprising:
applying a voltage to the diffusion region of at least one of the first select transistors, the NAND strings associated with a plurality of word lines, the magnitude of the voltage applied to the diffusion region depends on the location of a selected word line on the plurality of NAND strings; and
applying a program voltage to the selected word line while applying the voltage to the diffusion region.
2. The method of claim 1, wherein the voltage applied to the diffusion region of at least one of the first select transistors is a first voltage, and further comprising:
applying a second voltage to the diffusion region of the second select transistor of at least one of the NAND strings while applying the program voltage, the second voltage has a magnitude that depends on the location of the selected word line.
3. The method of claim 1, wherein the plurality of NAND strings are associated with a common source line, the diffusion region of the first select transistor is a contact of the respective NAND strings to the common source line.
4. The method of claim 3, wherein each of the plurality of NAND strings is associated with a bit line, the diffusion region of the second select transistor is a contact to a respective bit line of unselected NAND strings.
5. The method of claim 1, wherein each of the plurality of NAND strings is associated with a bit line, the diffusion region of the first select transistor is a contact to a respective bit line of unselected NAND strings.
6. The method of claim 1, further comprising:
applying a voltage to a gate of the first select transistor while applying the program voltage, the voltage applied to the gate depends on the location of the selected word line.
7. A non-volatile storage device comprising:
a plurality of NAND strings, each NAND string having a plurality of non-volatile storage elements over a channel, a first select transistor at a first end of the NAND string, and a second select transistor at a second end of the NAND string, the first and second select transistors each having a diffusion region on the opposite side of the select transistor from the channel of the NAND string;
a plurality of word lines associated with the plurality of NAND strings; and
one or more managing circuits in communication with the plurality of non-volatile NAND strings, and the plurality of word lines, the one or more managing circuits apply a voltage to the diffusion region of at least one of the first select transistors, the magnitude of the voltage applied to the diffusion region depends on the location of a selected word line on the plurality of NAND strings, the one or more managing circuits apply a program voltage to the selected word line while applying the voltage to the diffusion region of at least one of the first select transistors.
8. The non-volatile storage device of claim 7, wherein the voltage applied to the diffusion region is a first voltage, the one or more managing circuits apply a second voltage to a diffusion region of the second select transistor of at least one of the NAND strings while applying the program voltage, the second voltage has a magnitude that depends on the location of the selected word line.
9. The non-volatile storage device of claim 7, wherein the plurality of NAND strings are associated with a common source line, the diffusion region of the first select transistor is in electrical contact with the respective NAND strings to the common source line.
10. The non-volatile storage device of claim 9, wherein each of the plurality of NAND strings is associated with a bit line, the diffusion region of the second select transistor is in electrical contact to a respective bit line of unselected NAND strings.
11. The non-volatile storage device of claim 7, wherein each of the plurality of NAND strings is associated with a bit line, the diffusion region of the first select transistor is in electrical contact to a respective bit line of unselected NAND strings.
12. The non-volatile storage device of claim 7, wherein the one or more managing circuits apply a voltage to a gate of the first select transistor while applying the program voltage, the voltage applied to the gate depends on the location of the selected word line.
13. A method of operating non-volatile storage having a plurality of NAND strings associated with a plurality of word lines, each of the plurality of NAND strings associated with a first contact at a first end of a given NAND string and a second contact at a second end of a given NAND string, the method comprising:
applying a voltage that depends on the location of a selected word line of the plurality of word lines to the first contact associated with at least unselected NAND strings of the plurality of NAND strings; and
applying a program voltage to the selected word line while applying the voltage.
14. The method of claim 13, wherein each of the unselected NAND strings has a source select transistor and a drain select transistor, the applying a first voltage to the first contact of at least unselected NAND strings includes:
applying a first voltage to the first contact if the selected word line is in a first group of one or more of the word lines, applying a second voltage to the first contact if the selected word line is in a second group of one or more of the word lines, the first group is closer to the source select transistor than the second group, the first voltage is greater than the second voltage.
15. The method of claim 14, wherein the NAND strings are associated with a common source line, the first contact is a contact of the respective NAND strings to the common source line.
16. The method of claim 14, wherein each of the NAND strings is associated with a bit line, the first contact is a contact of the unselected NAND strings to a respective bit line.
17. The method of claim 13, wherein each of the unselected NAND strings is associated with a bit line, each of the unselected NAND strings has a source select transistor and a drain select transistor, the applying a voltage to the first contact includes:
applying a first voltage to bit lines of the unselected NAND strings if the selected word line is in a first group of one or more word lines, applying a second voltage to the bit lines of the unselected NAND strings if the selected word line is in a second group of one or more word lines, the first group is closer to the drain select transistor, the first voltage is greater in magnitude than the second voltage.
18. The method of claim 13, wherein the voltage applied to the first contact is a first voltage, and further comprising:
applying a second voltage to the second contact of the unselected NAND strings that depends on the location of the selected word line while applying the program voltage.
19. The method of claim 13, wherein at least three different voltages are applied to the first contact depending on the position of the selected word line.
20. A non-volatile storage device, comprising:
a plurality of NAND strings, each of the NAND strings have a plurality of non-volatile storage elements, a drain side select transistor, and a source side select transistor;
a plurality of word lines associated with the plurality of NAND strings;
a common source line coupled to the source side select transistors of the NAND strings;
a plurality of bit lines, each of the bit lines is coupled to the drain side select transistor associated with one of the NAND strings; and
one or more managing circuits in communication with the plurality of NAND strings, the plurality of word lines, the common source line, and the plurality of bit lines, the one or more managing circuits apply a first voltage that depends on the location of a selected word line of the plurality of word lines to either the bit lines associated with the drain side select transistors of inhibited NAND strings or the source line associated with the source side select transistors, the one or more managing circuits apply a program voltage to the selected word line while applying the first voltage.
21. The non-volatile storage device of claim 20, wherein the one or more managing circuits apply the first voltage to the common source line while applying the program voltage.
22. The non-volatile storage device of claim 20, wherein the one or more managing circuits apply the first voltage to the bit lines associated with the inhibited NAND strings while applying the program voltage.
23. A method of operating non-volatile storage having a plurality of NAND strings and a plurality of word lines associated with the plurality of NAND strings, the method comprising:
applying a voltage to a common source line having a magnitude that depends on the location of a selected word line on the plurality of NAND strings; and
applying a program voltage to the selected word line while applying the voltage to the common source line.
24. The method of claim 23, further comprising:
inhibiting certain NAND strings of the plurality of NAND strings from programming; and
applying a voltage to bit lines associated with the inhibited NAND strings having a magnitude that depends on the location of the selected word line while applying the program voltage.
25. The method of claim 24, wherein the voltage applied to the common source line is greater when the selected word line is an edge word line adjacent to the source end of the NAND strings than when the selected word line is another word line, the voltage applied to the bit lines associated with the inhibited NAND strings is greater when the selected word line is an edge word line adjacent to the source end of the NAND strings than when the selected word line is a middle word line.