1. A method of forming patterns, comprising:
providing a material layer covered by a patterned hard mask;
performing a pretreatment to transform the surface property of the patterned mask; and
after the pretreatment, patterning the material layer by taking the patterned hard mask as a mask.
2. The method of forming patterns of claim 1, wherein the pretreatment comprises a nitridation process, an oxidation process or a radiation-related chemical reaction process.
3. The method of forming patterns of claim 1, wherein the material layer comprises a semiconductive material.
4. The method of forming patterns of claim 1, wherein the material layer comprises a work function material.
5. The method of forming patterns of claim 1, wherein the patterned hard mask comprises a metal, a metal oxide or a metal nitride.
6. The method of forming patterns of claim 5, wherein the patterned hard mask further comprises a dielectric material.
7. The method of forming patterns of claim 5, wherein the patterned hard mask further comprises an organic material.
8. The method of forming patterns of claim 7, wherein the material layer is patterned in situ after the pretreatment is performed.
9. The method of forming patterns of claim 1, wherein one of the chemical property and the physical property of the patterned hard mask is changed after the pretreatment.
10. The method of forming patterns of claim 9, wherein the chemical property comprises the bonding character of the surface of the hard mask.
11. A method of forming patterns, comprising:
providing a material layer covered by a patterned hard mask comprising at least one metal-atom-containing material;
performing a pretreatment to transform the surface property of the patterned mask; and
after the pretreatment, performing an etching process to pattern the material layer by taking the patterned hard mask as a mask.
12. The method of forming patterns of claim 11, wherein the pretreatment comprises a nitridation process, an oxidation process or a radiation-related chemical reaction process.
13. The method of forming patterns of claim 12, wherein after the pretreatment, one of an oxide of the metal-atom-containing material and a nitride of the metal-atom-containing material is formed on the surface of the metal.
14. The method of forming patterns of claim 13, wherein the metal-atom-containing material is selected from the group consisting of titanium, titanium nitride, tantalum, lanthanum, rare earth elements, and transition elements.
15. The method of forming patterns of claim 11, wherein the etching process is performed in situ after the pretreatment is performed.
16. The method of forming patterns of claim 11, wherein the etching process is a plasma etching performed by using an etching tool.
17. The method of forming patterns of claim 16, wherein the distance between two electrodes of the etching tool is between 26 millimeters to 33 millimeters.
18. The method of forming patterns of claim 16, wherein the power of the etching tool is 50 watts or 150 watts and the frequency of the etching tool is 2 MHz, 27 Mhz or 60 Mhz.
19. The method of forming patterns of claim 11, wherein the etching process is performed with nitrogen flowing into the etching tool to serve as a carrier gas.
20. The method of forming patterns of claim 11, wherein the patterned hard mask comprises a silicon oxide layer, a silicon oxynitride layer, a titanium nitride layer and a titanium layer.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
What is claimed is:
1. A method of making semiconductor substrates suitable for making thin vertical current conducting devices comprising:
providing a relatively thick semiconducting substrate with at least one conductivity type having a thickness of from about 100 m to 700 m and having a first side and a second side opposite to the first side;
optionally forming at least one active device region on the first side of said relatively thick substrate;
thinning the semiconducting substrate in at least one selected region on the second side below at least partially where the active device will be on the first side so as to have the selected region thinned to a thickness ranging from about 10 m to 400 m to form at least one deep trench;
controlling the depth of the thinning of the semiconducting substrate when the substrate has more than one conductivity type layers or more than one conductivity type layer concentrations so that either (a) some of the first thinned conductivity type layer or some of the first thinned conductivity type layer concentration remains or (b) thinning all the way through the first conductivity type layer or all the way through the first conductivity type layer concentration;
optionally forming a conductivity type dopant in the semiconductor substrate in the thinned selected region on the second side;
forming a current electrode on the second side in contact with said thinned selected region or said conductivity type dopant in said thinned selected region; and
forming at least one active device region on the first side of said relatively thick substrate if it was not formed during the prior optional forming operation.
2. A method according to claim 1, wherein the thinning of the semiconducting substrate in the selected region is thinned to a thickness ranging from 10 m to 200 m.
3. A method according to claim 1, wherein the thinning is done by etching.
4. A method according to claim 3, wherein the etching is done by deep RIE, chemical etching, anisotropic chemical etching, XeF2 gas etching, plasma etching, or isotropic plasma etching.
5. A method according to claim 4, wherein the etching is done by deep RIE.
6. A method according to claim 1, wherein the thinning is done by laser drilling.
7. A method according to claim 1, wherein the conductivity type of the substrate is either a P conductivity type or an N conductivity type.
8. A method according to claim 1, wherein the active device region is made by forming at least one conductivity type dopant in said relatively thick substrate on said first side; and
forming a current electrode in contact with said at least one conductivity type dopant in said thick substrate on said first side.
9. A method according to claim 1, wherein the active device region formed on the first side is a source or a drain.
10. A method according to claim 9, wherein the active device region also has a gate electrode.
11. A method according to claim 9, wherein the gate electrode is a field effect transistor electrode.
12. A method according to claim 1, wherein the thinning of the semiconducting substrate in selected regions on the second side is performed in a pattern of deep trenches extending from the second side.
13. A method according to claim 12, wherein the thinning of the semiconducting substrate in selected regions on the second side is performed in a pattern of random orientated deep trenches extending from the second side.
14. A method according to claim 12, wherein the deep trenches are aligned to the active device regions on the first side.
15. A method according to claim 14, wherein the deep trenches are aligned to the active device regions on the first side by first photoimaging the active devices on the first side and then photoimaging the areas to be thinned on the second side in registery with the first photoimaging on the first side using photolithographic alignment techniques.
16. A method according to claim 14, wherein the deep trenches are aligned to the active device regions on the first side by forming active device regions on the first side registered to the peripheral geometry of the semiconductor substrate and then forming trenches on the second side of the semiconductor substrate by registering the peripheral geometry of the semiconductor substrate so that it is registered to the first side.
17. A method according to claim 12, wherein there are more than one active device regions on the first side and the deep trenches are aligned to the active device regions to leave thick regions or ribs of support on the second side between each pair of active device regions on the first side.
18. A method according to claim 12, wherein the pattern of the series of deep trenches from the second side is formed in a non-contiguous pattern to provide increased substrate mechanical strength.
19. A method according to claim 18, wherein the non-contiguous pattern is a checkerboard pattern.
20. A method according to claim 1, wherein the relatively thick semiconductor substrate is made by float zone production.
21. A method according to claim 20, wherein the relatively thick semiconductor substrate is made of at least two layers having different conductivity dopant concentrations or conductivity dopant types.
22. A method according to claim 21, wherein the relatively thick semiconductor substrate is made by wafer bonding.
23. A method according to claim 21, wherein one of the layers is made by epitaxial growth.
24. A method according to claim 1, wherein a vertical current MOSFET is made by providing as the relatively thick semiconductor substrate a composite of an N semiconductor substrate on which an N epi layer is formed to be the first side, and thinning the second side in selected regions to an extent that the thinning does not go all the way through the N substrate, whereby the on-resistance due to the N substrate is reduced.
25. A method according to claim 1, wherein a vertical current high voltage MOSFET is made by providing as the relatively thick semiconductor substrate a float zone N silicon substrate; and
forming an N conductivity type implant in the semiconductor substrate in the thinned selected regions on the second side.
26. A method according to claim 1, wherein a vertical current IGBT is made by
providing as the relatively thick semiconductor substrate a float zone N silicon substrate; and
forming a P conductivity type implant in the semiconductor substrate in the thinned selected regions on the second side.
27. A method according to claim 26, wherein prior to forming said P conductivity type implant on the thinned second side an N implant is first implanted into the thinned region on the second side to form an N buffer.
28. A method according to claim 26, wherein the P conductivity type implant is controlled to be a low doped, thin P type implant which functions as a transparent emitter to allow for the transport of electrons through the transparent emitter to the metal contact.
29. A method according to claim 1, wherein a diode is made by providing as the relatively thick semiconductor substrate a composite of an N substrate on which an N epi layer is formed to be the first side; and
thinning the second side in selected regions to an extent that the thinning does not go all the way through the N substrate.
30. A method according to claim 1, wherein a diode is made by
providing as the relatively thick semiconductor substrate a float zone N silicon substrate; and
forming a P conductivity type implant in the semiconductor substrate in the thinned selected regions on the second side.
31. A physically strong thin vertical current conducting device comprising:
a relatively thick semiconducting substrate with at least one conductivity type having a thickness of from about 100 m to 700 m and having a first side and a second side opposite to the first side;
at least one active device region on the first side of said relatively thick substrate;
at least one thinned selected region on the second side below the active device on the first side which has been thinned to a thickness ranging from about 10 m to 400 m to form at least one deep trench;
optionally providing a conductivity type dopant in the semiconductor substrate in the thinned selected region on the second side; and
a current electrode on the second side in contact with said thinned selected region or said conductivity type dopant in said thinned selected region;
whereby the device has physical stability in the regions of the remaining relatively thick substrate and
whereby in the thinned region below the active device vertical current can more readily conduct to provide improved electrical properties.
32. A physically strong thin vertical current conducting device according to claim 31, wherein the substrate has more than one conductivity type layers or more than one conductivity type layer concentrations and the depth of thinning is controlled so that either (a) some of the first thinned substrate layer remains or (b) the thinning is all the way through the first layer or first layer concentration.